src/soc/fu/mmu/pipe_data.py

   1 """MMU Pipeline Data structures
   2
   3 Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.
   4
   5 Interestingly none of the MMU instructions use RA, they all use RB.
   6 except dcbz which uses (RA|0)
   7
   8 Links:
   9 * https://bugs.libre-soc.org/show_bug.cgi?id=491
  10 * https://libre-soc.org/3d_gpu/architecture/regfile/
  11 """
  12
  13 from soc.fu.pipe_data import FUBaseData
  14 from soc.fu.mmu.mmu_input_record import CompMMUOpSubset
  15 from soc.fu.alu.pipe_data import CommonPipeSpec
  16
  17
  18 class MMUInputData(FUBaseData):
  19     regspec = [('INT', 'ra', '0:63'),        # RA
  20                ('INT', 'rb', '0:63'),        # RB
  21                ('SPR', 'spr1', '0:63'),      # MMU (slow)
  22                ]
  23     def __init__(self, pspec):
  24         super().__init__(pspec, False)
  25         # convenience
  26         self.a = self.ra
  27         self.b = self.rb
  28
  29
  30 class MMUOutputData(FUBaseData):
  31     regspec = [('INT', 'o', '0:63'),        # RT
  32                ('SPR', 'spr1', '0:63'),     # MMU (slow)
  33                ]
  34     def __init__(self, pspec):
  35         super().__init__(pspec, True)
  36
  37
  38 class MMUPipeSpec(CommonPipeSpec):
  39     regspec = (MMUInputData.regspec, MMUOutputData.regspec)
  40     opsubsetkls = CompMMUOpSubset