src/soc/fu/mmu/test/test_issuer_mmu_data_path.py

   1 from nmigen import Module, Signal
   2 from soc.simple.test.test_issuer import TestRunner
   3 from soc.simulator.program import Program
   4 from soc.config.endian import bigendian
   5 import unittest
   6
   7 from soc.fu.test.common import (
   8     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
   9
  10 # this test case takes about half a minute to run on my Talos II
  11 class MMUTestCase(TestAccumulatorBase):
  12     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  13     # libre-soc has own SPR unit
  14     # other instructions here -> must be load/store
  15
  16     def case_mmu_ldst(self):
  17         lst = [
  18                 "dcbz 1,2",
  19                 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
  20                 "mtspr 18, 1",     # reg 1 to DSISR
  21                 "mtspr 19, 2",     # reg 2 to DAR
  22                 "mfspr 1, 18",     # DSISR to reg 1
  23                 "mfspr 2, 19",     # DAR to reg 2
  24                 "lhz 3, 0(1)"      # load some data
  25               ]
  26
  27         initial_regs = [0] * 32
  28         #initial_regs[1] = 0xDEADBEEF
  29
  30         #FIXME initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
  31         initial_sprs = {}
  32         self.add_case(Program(lst, bigendian),
  33                       initial_regs, initial_sprs)
  34
  35
  36 if __name__ == "__main__":
  37     unittest.main(exit=False)
  38     suite = unittest.TestSuite()
  39     suite.addTest(TestRunner(MMUTestCase().test_data,microwatt_mmu=True))
  40     runner = unittest.TextTestRunner()
  41     runner.run(suite)