src/soc/fu/mmu/test/test_issuer_mmu_data_path.py

   1 from nmigen import Module, Signal
   2 from soc.simple.test.test_issuer import TestRunner
   3 from openpower.simulator.program import Program
   4 from openpower.endian import bigendian
   5 import unittest
   6
   7 from openpower.test.common import (
   8     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
   9
  10 # this test case takes about half a minute to run on my Talos II
  11 class MMUTestCase(TestAccumulatorBase):
  12     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  13     # libre-soc has own SPR unit
  14     # other instructions here -> must be load/store
  15
  16     def cse_dcbz(self):
  17         lst = [
  18                 "dcbz 1,2",
  19               ]
  20
  21         initial_regs = [0] * 32
  22         initial_regs[1] = 0x2
  23         initial_regs[2] = 0x2020
  24
  25         self.add_case(Program(lst, bigendian),
  26                       initial_regs, initial_mem={})
  27
  28     def case_mmu_dar(self):
  29         lst = [
  30                 "mfspr 1, 720",     # DAR to reg 1
  31                 "mtspr 19, 3",      # reg 3 to DAR
  32               ]
  33
  34         initial_regs = [0] * 32
  35         initial_regs[1] = 0x2
  36         initial_regs[3] = 0x5
  37
  38         initial_sprs = {'DAR': 0x87654321,
  39                         }
  40         self.add_case(Program(lst, bigendian),
  41                       initial_regs, initial_sprs, initial_mem={})
  42
  43     def case_mmu_ldst(self):
  44         lst = [
  45                 "dcbz 1,0",
  46                 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
  47                 "mtspr 18, 1",     # reg 1 to DSISR
  48                 "mtspr 19, 2",     # reg 2 to DAR
  49                 "mfspr 5, 18",     # DSISR to reg 5
  50                 "mfspr 6, 19",     # DAR to reg 6
  51                 "mtspr 48, 3",    # set MMU PID
  52                 "mtspr 720, 4",    # set MMU PRTBL
  53                 "lhz 3, 0(1)",     # load some data
  54                 "addi 7, 0, 1"
  55               ]
  56
  57         initial_regs = [0] * 32
  58         initial_regs[1] = 0x2
  59         initial_regs[2] = 0x2020
  60         initial_regs[3] = 5
  61         initial_regs[4] = 0xDEADBEEF
  62
  63         initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321,
  64                         'PIDR': 0xabcd, 'PRTBL': 0x0def}
  65         self.add_case(Program(lst, bigendian),
  66                       initial_regs, initial_sprs, initial_mem={})
  67
  68
  69 if __name__ == "__main__":
  70     mem = {}
  71     unittest.main(exit=False)
  72     suite = unittest.TestSuite()
  73     suite.addTest(TestRunner(MMUTestCase().test_data,
  74                              microwatt_mmu=True,
  75                              svp64=False,
  76                              rom=mem))
  77     runner = unittest.TextTestRunner()
  78     runner.run(suite)