src/soc/fu/mmu/test/test_issuer_mmu_rom.py

   1 from nmigen import Module, Signal
   2 from soc.simple.test.test_runner import TestRunner
   3 from soc.simulator.program import Program
   4 from soc.config.endian import bigendian
   5 import unittest
   6
   7 from soc.fu.test.common import (TestAccumulatorBase, skip_case, TestCase,
   8                                 ALUHelpers)
   9
  10 def b(x):
  11     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  12                           byteorder='big', signed=False)
  13
  14
  15 default_mem = { 0x10000:    # PARTITION_TABLE_2
  16                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  17                 b(0x800000000100000b),
  18
  19                 0x30000:     # RADIX_ROOT_PTE
  20                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  21                 b(0x8000000000040009),
  22
  23                 0x40000:     # RADIX_SECOND_LEVEL
  24                         #          V = 1 L = 1 SW = 0 RPN = 0
  25                            # R = 1 C = 1 ATT = 0 EAA 0x7
  26                 b(0xc000000000000187),
  27
  28                 0x1000000:   # PROCESS_TABLE_3
  29                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  30                 b(0x40000000000300ad),
  31             }
  32
  33
  34 class MMUTestCase(TestAccumulatorBase):
  35     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  36     # libre-soc has own SPR unit
  37     # libre-soc MMU supports MTSPR and MFSPR but **ONLY** for the subset
  38     # of SPRs it actually does.
  39     # other instructions here -> must be load/store
  40
  41     def case_mmu_ldst(self):
  42         lst = [
  43                 #"mtspr 720, 1", # XXX do not execute unsupported instructions
  44                 "lhz 3, 0(1)"      # load some data
  45               ]
  46
  47         initial_regs = [0] * 32
  48
  49         # set process table
  50         prtbl = 0x1000000
  51         initial_regs[1] = prtbl
  52
  53         initial_sprs = {'DSISR': 0, 'DAR': 0,
  54                          720: 0}
  55         self.add_case(Program(lst, bigendian),
  56                       initial_regs, initial_sprs)
  57
  58
  59
  60
  61 if __name__ == "__main__":
  62     unittest.main(exit=False)
  63     suite = unittest.TestSuite()
  64     suite.addTest(TestRunner(MMUTestCase().test_data, microwatt_mmu=True,
  65                              rom=default_mem))
  66     runner = unittest.TextTestRunner()
  67     runner.run(suite)
  68
  69 #  soc/simple/test/test_runner.py