1 from nmigen
import Module
, Signal
3 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
5 from nmigen
.cli
import rtlil
7 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
8 from soc
.decoder
.power_decoder
import (create_pdecode
)
9 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
10 from soc
.decoder
.power_enums
import (XER_bits
, Function
, MicrOp
, CryIn
)
11 from soc
.decoder
.selectable_int
import SelectableInt
12 from soc
.simulator
.program
import Program
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.config
.endian
import bigendian
15 from soc
.consts
import MSR
18 from soc
.fu
.test
.common
import (
19 TestAccumulatorBase
, skip_case
, TestCase
, ALUHelpers
)
22 from soc
.fu
.div
.test
.helper
import (log_rand
, get_cu_inputs
,
23 set_alu_inputs
, DivTestHelper
)
25 from soc
.simple
.core
import NonProductionCore
26 from soc
.config
.test
.test_loadstore
import TestMemPspec
27 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
33 class MMUTestCase(TestAccumulatorBase
):
34 # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
35 # other instructions here -> must be load/store
37 def case_mfspr_after_invalid_load(self
):
38 lst
= [ # TODO -- set SPR on both sinulator and port interface
39 "mfspr 1, 18", # DSISR to reg 1
40 "mfspr 2, 19", # DAR to reg 2
41 # TODO -- verify returned sprvals
44 initial_regs
= [0] * 32
46 #THOSE are currently broken -- initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
48 self
.add_case(Program(lst
, bigendian
),
49 initial_regs
, initial_sprs
)
51 #def case_ilang(self):
52 # pspec = SPRPipeSpec(id_wid=2)
53 # alu = SPRBasePipe(pspec)
54 # vl = rtlil.convert(alu, ports=alu.ports())
55 # with open("trap_pipeline.il", "w") as f:
59 class TestRunner(unittest
.TestCase
):
60 def __init__(self
, test_data
):
61 super().__init
__("run_all")
62 self
.test_data
= test_data
64 def execute(self
, core
, instruction
, pdecode2
, test
):
65 program
= test
.program
66 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
69 gen
= program
.generate_instructions()
70 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
75 while index
< len(instructions
):
76 ins
, code
= instructions
[index
]
78 print("pc %08x instr: %08x" % (pc
, ins
& 0xffffffff))
82 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
83 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
84 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
85 print("before: so/ov/32", so
, ov
, ov32
)
87 # ask the decoder to decode this binary data (endian'd)
88 yield pdecode2
.dec
.bigendian
.eq(bigendian
) # little / big?
89 yield pdecode2
.state
.msr
.eq(msr
) # set MSR in pdecode2
90 yield pdecode2
.state
.pc
.eq(pc
) # set PC in pdecode2
91 yield instruction
.eq(ins
) # raw binary instr.
94 yield from setup_regs(pdecode2
, core
, test
)
96 opname
= code
.split(' ')[0]
97 yield from sim
.call(opname
)
101 print("pc after %08x" % (pc
))
103 fsm
= core
.fus
.fus
["mmu0"].alu
105 vld
= yield fsm
.n
.valid_o
108 if debughang
: print("not valid -- hang")
109 vld
= yield fsm
.n
.valid_o
110 if debughang
==2: vld
=1
116 instruction
= Signal(32)
118 pdecode
= create_pdecode()
120 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
122 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
128 m
.submodules
.core
= core
= NonProductionCore(pspec
,microwatt_mmu
=True)
130 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
136 for test
in self
.test_data
:
137 print("test", test
.name
)
138 print("sprs", test
.sprs
)
139 program
= test
.program
140 with self
.subTest(test
.name
):
141 yield from self
.execute(core
, instruction
, pdecode2
, test
)
143 sim
.add_sync_process(process
)
144 with sim
.write_vcd("mmu_ldst_simulator.vcd", "mmu_ldst_simulator.gtkw",
148 if __name__
== "__main__":
149 unittest
.main(exit
=False)
150 suite
= unittest
.TestSuite()
151 suite
.addTest(TestRunner(MMUTestCase().test_data
))
153 runner
= unittest
.TextTestRunner()