src/soc/fu/mul/formal/proof_main_stage.py

   1 # Proof of correctness for partitioned equal signal combiner
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3
   4 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
   5                     signed)
   6 from nmigen.asserts import Assert, AnyConst, Assume, Cover
   7 from nmigen.test.utils import FHDLTestCase
   8 from nmigen.cli import rtlil
   9
  10 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
  11 from soc.fu.alu.pipe_data import ALUPipeSpec
  12 from soc.fu.alu.alu_input_record import CompALUOpSubset
  13 from soc.decoder.power_enums import InternalOp
  14 import unittest
  15
  16
  17 # This defines a module to drive the device under test and assert
  18 # properties about its outputs
  19 class Driver(Elaboratable):
  20     def __init__(self):
  21         # inputs and outputs
  22         pass
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27
  28         rec = CompALUOpSubset()
  29         recwidth = 0
  30         # Setup random inputs for dut.op
  31         for p in rec.ports():
  32             width = p.width
  33             recwidth += width
  34             comb += p.eq(AnyConst(width))
  35
  36         pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
  37         m.submodules.dut = dut = ShiftRotMainStage(pspec)
  38
  39         # convenience variables
  40         a = dut.i.rs
  41         b = dut.i.rb
  42         ra = dut.i.ra
  43         carry_in = dut.i.xer_ca[0]
  44         carry_in32 = dut.i.xer_ca[1]
  45         so_in = dut.i.xer_so
  46         carry_out = dut.o.xer_ca
  47         o = dut.o.o
  48
  49         # setup random inputs
  50         comb += [a.eq(AnyConst(64)),
  51                  b.eq(AnyConst(64)),
  52                  carry_in.eq(AnyConst(1)),
  53                  carry_in32.eq(AnyConst(1)),
  54                  so_in.eq(AnyConst(1))]
  55
  56         comb += dut.i.ctx.op.eq(rec)
  57
  58         # Assert that op gets copied from the input to output
  59         for rec_sig in rec.ports():
  60             name = rec_sig.name
  61             dut_sig = getattr(dut.o.ctx.op, name)
  62             comb += Assert(dut_sig == rec_sig)
  63
  64         # signed and signed/32 versions of input a
  65         a_signed = Signal(signed(64))
  66         a_signed_32 = Signal(signed(32))
  67         comb += a_signed.eq(a)
  68         comb += a_signed_32.eq(a[0:32])
  69
  70         # main assertion of arithmetic operations
  71         with m.Switch(rec.insn_type):
  72             with m.Case(InternalOp.OP_SHL):
  73                 comb += Assume(ra == 0)
  74                 with m.If(rec.is_32bit):
  75                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
  76                     comb += Assert(o[32:64] == 0)
  77                 with m.Else():
  78                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
  79             with m.Case(InternalOp.OP_SHR):
  80                 comb += Assume(ra == 0)
  81                 with m.If(~rec.is_signed):
  82                     with m.If(rec.is_32bit):
  83                         comb += Assert(o[0:32] == (a[0:32] >> b[0:6]))
  84                         comb += Assert(o[32:64] == 0)
  85                     with m.Else():
  86                         comb += Assert(o == (a >> b[0:7]))
  87                 with m.Else():
  88                     with m.If(rec.is_32bit):
  89                         comb += Assert(o[0:32] == (a_signed_32 >> b[0:6]))
  90                         comb += Assert(o[32:64] == Repl(a[31], 32))
  91                     with m.Else():
  92                         comb += Assert(o == (a_signed >> b[0:7]))
  93
  94         return m
  95
  96
  97 class ALUTestCase(FHDLTestCase):
  98     def test_formal(self):
  99         module = Driver()
 100         self.assertFormal(module, mode="bmc", depth=2)
 101         self.assertFormal(module, mode="cover", depth=2)
 102     def test_ilang(self):
 103         dut = Driver()
 104         vl = rtlil.convert(dut, ports=[])
 105         with open("main_stage.il", "w") as f:
 106             f.write(vl)
 107
 108
 109 if __name__ == '__main__':
 110     unittest.main()