rename InternalOp to MicrOp
[soc.git] / src / soc / fu / mul / mul_input_record.py
1 from nmigen.hdl.rec import Record, Layout
2
3 from soc.decoder.power_enums import MicrOp, Function, CryIn
4
5
6 class CompMULOpSubset(Record):
7 """CompMULOpSubset
8
9 a copy of the relevant subset information from Decode2Execute1Type
10 needed for MUL operations. use with eq_from_execute1 (below) to
11 grab subsets.
12 """
13 def __init__(self, name=None):
14 layout = (('insn_type', MicrOp),
15 ('fn_unit', Function),
16 ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
17 ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
18 ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
19 ('invert_a', 1),
20 ('zero_a', 1),
21 ('invert_out', 1),
22 ('write_cr0', 1),
23 ('is_32bit', 1),
24 ('is_signed', 1),
25 ('insn', 32),
26 )
27
28 Record.__init__(self, Layout(layout), name=name)
29
30 # grrr. Record does not have kwargs
31 self.insn_type.reset_less = True
32 self.fn_unit.reset_less = True
33 self.zero_a.reset_less = True
34 self.invert_a.reset_less = True
35 self.invert_out.reset_less = True
36 self.is_32bit.reset_less = True
37 self.is_signed.reset_less = True
38
39 def eq_from_execute1(self, other):
40 """ use this to copy in from Decode2Execute1Type
41 """
42 res = []
43 for fname, sig in self.fields.items():
44 eqfrom = other.do.fields[fname]
45 res.append(sig.eq(eqfrom))
46 return res
47
48 def ports(self):
49 return [self.insn_type,
50 self.invert_a,
51 self.invert_out,
52 self.is_32bit,
53 self.is_signed,
54 ]