src/soc/fu/mul/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.mul.pipeline import MulBasePipe
  17 from soc.fu.mul.pipe_data import MulPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to MulFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  29     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  30
  31     print ("alu get_cu_inputs", res)
  32
  33     return res
  34
  35
  36
  37 def set_alu_inputs(alu, dec2, sim):
  38     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  39     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  40     # and place it into data_i.b
  41
  42     inp = yield from get_cu_inputs(dec2, sim)
  43     print ("set alu inputs", inp)
  44     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  45     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  46
  47     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  49
  50
  51 # This test bench is a bit different than is usual. Initially when I
  52 # was writing it, I had all of the tests call a function to create a
  53 # device under test and simulator, initialize the dut, run the
  54 # simulation for ~2 cycles, and assert that the dut output what it
  55 # should have. However, this was really slow, since it needed to
  56 # create and tear down the dut and simulator for every test case.
  57
  58 # Now, instead of doing that, every test case in MulTestCase puts some
  59 # data into the test_data list below, describing the instructions to
  60 # be tested and the initial state. Once all the tests have been run,
  61 # test_data gets passed to TestRunner which then sets up the DUT and
  62 # simulator once, runs all the data through it, and asserts that the
  63 # results match the pseudocode sim at every cycle.
  64
  65 # By doing this, I've reduced the time it takes to run the test suite
  66 # massively. Before, it took around 1 minute on my computer, now it
  67 # takes around 3 seconds
  68
  69
  70 class MulTestCase(FHDLTestCase):
  71     test_data = []
  72
  73     def __init__(self, name):
  74         super().__init__(name)
  75         self.test_name = name
  76
  77     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  78         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  79         self.test_data.append(tc)
  80
  81     def tst_0_mullw(self):
  82         lst = [f"mullw 3, 1, 2"]
  83         initial_regs = [0] * 32
  84         #initial_regs[1] = 0xffffffffffffffff
  85         #initial_regs[2] = 0xffffffffffffffff
  86         initial_regs[1] = 0x2ffffffff
  87         initial_regs[2] = 0x2
  88         self.run_tst_program(Program(lst), initial_regs)
  89
  90     def tst_1_mullwo_(self):
  91         lst = [f"mullwo. 3, 1, 2"]
  92         initial_regs = [0] * 32
  93         initial_regs[1] = 0x3b34b06f
  94         initial_regs[2] = 0xfdeba998
  95         self.run_tst_program(Program(lst), initial_regs)
  96
  97     def tst_2_mullwo(self):
  98         lst = [f"mullwo 3, 1, 2"]
  99         initial_regs = [0] * 32
 100         initial_regs[1] = 0xffffffffffffa988 # -5678
 101         initial_regs[2] = 0xffffffffffffedcc # -1234
 102         self.run_tst_program(Program(lst), initial_regs)
 103
 104     def tst_3_mullw(self):
 105         lst = ["mullw 3, 1, 2",
 106                "mullw 3, 1, 2"]
 107         initial_regs = [0] * 32
 108         initial_regs[1] = 0x6
 109         initial_regs[2] = 0xe
 110         self.run_tst_program(Program(lst), initial_regs)
 111
 112     def test_4_mullw_rand(self):
 113         for i in range(40):
 114             lst = ["mullw 3, 1, 2"]
 115             initial_regs = [0] * 32
 116             initial_regs[1] = random.randint(0, (1<<64)-1)
 117             initial_regs[2] = random.randint(0, (1<<64)-1)
 118             self.run_tst_program(Program(lst), initial_regs)
 119
 120     def test_4_mullw_nonrand(self):
 121         for i in range(40):
 122             lst = ["mullw 3, 1, 2"]
 123             initial_regs = [0] * 32
 124             initial_regs[1] = i+1
 125             initial_regs[2] = i+20
 126             self.run_tst_program(Program(lst), initial_regs)
 127
 128     def tst_rand_mullw(self):
 129         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
 130         for i in range(40):
 131             choice = random.choice(insns)
 132             lst = [f"{choice} 3, 1, 2"]
 133             initial_regs = [0] * 32
 134             initial_regs[1] = random.randint(0, (1<<64)-1)
 135             initial_regs[2] = random.randint(0, (1<<64)-1)
 136             self.run_tst_program(Program(lst), initial_regs)
 137
 138     def test_ilang(self):
 139         pspec = MulPipeSpec(id_wid=2)
 140         alu = MulBasePipe(pspec)
 141         vl = rtlil.convert(alu, ports=alu.ports())
 142         with open("mul_pipeline.il", "w") as f:
 143             f.write(vl)
 144
 145
 146 class TestRunner(FHDLTestCase):
 147     def __init__(self, test_data):
 148         super().__init__("run_all")
 149         self.test_data = test_data
 150
 151     def run_all(self):
 152         m = Module()
 153         comb = m.d.comb
 154         instruction = Signal(32)
 155
 156         pdecode = create_pdecode()
 157
 158         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 159
 160         pspec = MulPipeSpec(id_wid=2)
 161         m.submodules.alu = alu = MulBasePipe(pspec)
 162
 163         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 164         comb += alu.n.ready_i.eq(1)
 165         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 166         sim = Simulator(m)
 167
 168         sim.add_clock(1e-6)
 169         def process():
 170             for test in self.test_data:
 171                 print(test.name)
 172                 program = test.program
 173                 self.subTest(test.name)
 174                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 175                                 test.mem, test.msr)
 176                 gen = program.generate_instructions()
 177                 instructions = list(zip(gen, program.assembly.splitlines()))
 178                 yield Settle()
 179
 180                 index = sim.pc.CIA.value//4
 181                 while index < len(instructions):
 182                     ins, code = instructions[index]
 183
 184                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 185                     print(code)
 186                     if 'XER' in sim.spr:
 187                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 188                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 189                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 190                         print ("before: so/ov/32", so, ov, ov32)
 191
 192                     # ask the decoder to decode this binary data (endian'd)
 193                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 194                     yield instruction.eq(ins)          # raw binary instr.
 195                     yield Settle()
 196                     fn_unit = yield pdecode2.e.do.fn_unit
 197                     self.assertEqual(fn_unit, Function.MUL.value)
 198                     yield from set_alu_inputs(alu, pdecode2, sim)
 199
 200                     # set valid for one cycle, propagate through pipeline...
 201                     yield alu.p.valid_i.eq(1)
 202                     yield
 203                     yield alu.p.valid_i.eq(0)
 204
 205                     opname = code.split(' ')[0]
 206                     yield from sim.call(opname)
 207                     index = sim.pc.CIA.value//4
 208
 209                     # ...wait for valid to pop out the end
 210                     vld = yield alu.n.valid_o
 211                     while not vld:
 212                         yield
 213                         vld = yield alu.n.valid_o
 214                     yield
 215
 216                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 217                     yield Settle()
 218
 219         sim.add_sync_process(process)
 220         with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
 221                             traces=[]):
 222             sim.run()
 223
 224     def check_alu_outputs(self, alu, dec2, sim, code):
 225
 226         rc = yield dec2.e.do.rc.data
 227         cridx_ok = yield dec2.e.write_cr.ok
 228         cridx = yield dec2.e.write_cr.data
 229
 230         print ("check extra output", repr(code), cridx_ok, cridx)
 231         if rc:
 232             self.assertEqual(cridx, 0, code)
 233
 234         oe = yield dec2.e.do.oe.oe
 235         oe_ok = yield dec2.e.do.oe.ok
 236         if not oe or not oe_ok:
 237             # if OE not enabled, XER SO and OV must correspondingly be false
 238             so_ok = yield alu.n.data_o.xer_so.ok
 239             ov_ok = yield alu.n.data_o.xer_ov.ok
 240             self.assertEqual(so_ok, False, code)
 241             self.assertEqual(ov_ok, False, code)
 242
 243         sim_o = {}
 244         res = {}
 245
 246         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 247         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 248         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 249         yield from ALUHelpers.get_int_o(res, alu, dec2)
 250         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 251
 252         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 253         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 254         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 255         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 256         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 257
 258         ALUHelpers.check_int_o(self, res, sim_o, code)
 259         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 260         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 261         ALUHelpers.check_xer_so(self, res, sim_o, code)
 262         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 263
 264
 265 if __name__ == "__main__":
 266     unittest.main(exit=False)
 267     suite = unittest.TestSuite()
 268     suite.addTest(TestRunner(MulTestCase.test_data))
 269
 270     runner = unittest.TextTestRunner()
 271     runner.run(suite)