1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import (TestCase
, ALUHelpers
)
16 from soc
.fu
.mul
.pipeline
import MulBasePipe
17 from soc
.fu
.mul
.pipe_data
import MulPipeSpec
21 def get_cu_inputs(dec2
, sim
):
22 """naming (res) must conform to MulFunctionUnit input regspec
26 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
27 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
28 yield from ALUHelpers
.get_rd_sim_xer_ca(res
, sim
, dec2
) # XER.ca
29 yield from ALUHelpers
.get_sim_xer_so(res
, sim
, dec2
) # XER.so
31 print ("alu get_cu_inputs", res
)
37 def set_alu_inputs(alu
, dec2
, sim
):
38 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
39 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
40 # and place it into data_i.b
42 inp
= yield from get_cu_inputs(dec2
, sim
)
43 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
44 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
46 yield from ALUHelpers
.set_xer_ca(alu
, dec2
, inp
)
47 yield from ALUHelpers
.set_xer_so(alu
, dec2
, inp
)
50 # This test bench is a bit different than is usual. Initially when I
51 # was writing it, I had all of the tests call a function to create a
52 # device under test and simulator, initialize the dut, run the
53 # simulation for ~2 cycles, and assert that the dut output what it
54 # should have. However, this was really slow, since it needed to
55 # create and tear down the dut and simulator for every test case.
57 # Now, instead of doing that, every test case in MulTestCase puts some
58 # data into the test_data list below, describing the instructions to
59 # be tested and the initial state. Once all the tests have been run,
60 # test_data gets passed to TestRunner which then sets up the DUT and
61 # simulator once, runs all the data through it, and asserts that the
62 # results match the pseudocode sim at every cycle.
64 # By doing this, I've reduced the time it takes to run the test suite
65 # massively. Before, it took around 1 minute on my computer, now it
66 # takes around 3 seconds
69 class MulTestCase(FHDLTestCase
):
72 def __init__(self
, name
):
73 super().__init
__(name
)
76 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
77 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
)
78 self
.test_data
.append(tc
)
80 def test_0_mullw(self
):
81 lst
= [f
"mullw 3, 1, 2"]
82 initial_regs
= [0] * 32
83 #initial_regs[1] = 0xffffffffffffffff
84 #initial_regs[2] = 0xffffffffffffffff
85 initial_regs
[1] = 0x2ffffffff
87 self
.run_tst_program(Program(lst
), initial_regs
)
89 def tst_1_mullwo_(self
):
90 lst
= [f
"mullwo. 3, 1, 2"]
91 initial_regs
= [0] * 32
92 initial_regs
[1] = 0x3b34b06f
93 initial_regs
[2] = 0xfdeba998
94 self
.run_tst_program(Program(lst
), initial_regs
)
96 def tst_2_mullwo_(self
):
97 lst
= [f
"mullwo. 3, 1, 2"]
98 initial_regs
= [0] * 32
99 initial_regs
[1] = 0xffffffffffffa988 # -5678
100 initial_regs
[2] = 0xffffffffffffedcc # -1234
101 self
.run_tst_program(Program(lst
), initial_regs
)
103 def test_3_mullw(self
):
105 lst
= ["mullw 3, 1, 2"]
106 initial_regs
= [0] * 32
107 initial_regs
[1] = random
.randint(0, (1<<64)-1)
108 initial_regs
[2] = random
.randint(0, (1<<64)-1)
109 self
.run_tst_program(Program(lst
), initial_regs
)
111 def tst_rand_mullw(self
):
112 insns
= ["mullw", "mullw.", "mullwo", "mullwo."]
114 choice
= random
.choice(insns
)
115 lst
= [f
"{choice} 3, 1, 2"]
116 initial_regs
= [0] * 32
117 initial_regs
[1] = random
.randint(0, (1<<64)-1)
118 initial_regs
[2] = random
.randint(0, (1<<64)-1)
119 self
.run_tst_program(Program(lst
), initial_regs
)
121 def test_ilang(self
):
122 pspec
= MulPipeSpec(id_wid
=2)
123 alu
= MulBasePipe(pspec
)
124 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
125 with
open("mul_pipeline.il", "w") as f
:
129 class TestRunner(FHDLTestCase
):
130 def __init__(self
, test_data
):
131 super().__init
__("run_all")
132 self
.test_data
= test_data
137 instruction
= Signal(32)
139 pdecode
= create_pdecode()
141 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
143 pspec
= MulPipeSpec(id_wid
=2)
144 m
.submodules
.alu
= alu
= MulBasePipe(pspec
)
146 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
147 comb
+= alu
.p
.valid_i
.eq(1)
148 comb
+= alu
.n
.ready_i
.eq(1)
149 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
154 for test
in self
.test_data
:
156 program
= test
.program
157 self
.subTest(test
.name
)
158 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
160 gen
= program
.generate_instructions()
161 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
163 index
= sim
.pc
.CIA
.value
//4
164 while index
< len(instructions
):
165 ins
, code
= instructions
[index
]
167 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
170 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
171 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
172 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
173 print ("before: so/ov/32", so
, ov
, ov32
)
175 # ask the decoder to decode this binary data (endian'd)
176 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
177 yield instruction
.eq(ins
) # raw binary instr.
179 fn_unit
= yield pdecode2
.e
.do
.fn_unit
180 self
.assertEqual(fn_unit
, Function
.MUL
.value
)
181 yield from set_alu_inputs(alu
, pdecode2
, sim
)
183 opname
= code
.split(' ')[0]
184 yield from sim
.call(opname
)
185 index
= sim
.pc
.CIA
.value
//4
187 vld
= yield alu
.n
.valid_o
190 vld
= yield alu
.n
.valid_o
193 yield from self
.check_alu_outputs(alu
, pdecode2
, sim
, code
)
195 sim
.add_sync_process(process
)
196 with sim
.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
200 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
202 rc
= yield dec2
.e
.do
.rc
.data
203 cridx_ok
= yield dec2
.e
.write_cr
.ok
204 cridx
= yield dec2
.e
.write_cr
.data
206 print ("check extra output", repr(code
), cridx_ok
, cridx
)
208 self
.assertEqual(cridx
, 0, code
)
210 oe
= yield dec2
.e
.do
.oe
.oe
211 oe_ok
= yield dec2
.e
.do
.oe
.ok
212 if not oe
or not oe_ok
:
213 # if OE not enabled, XER SO and OV must correspondingly be false
214 so_ok
= yield alu
.n
.data_o
.xer_so
.ok
215 ov_ok
= yield alu
.n
.data_o
.xer_ov
.ok
216 self
.assertEqual(so_ok
, False, code
)
217 self
.assertEqual(ov_ok
, False, code
)
222 yield from ALUHelpers
.get_cr_a(res
, alu
, dec2
)
223 yield from ALUHelpers
.get_xer_ov(res
, alu
, dec2
)
224 yield from ALUHelpers
.get_xer_ca(res
, alu
, dec2
)
225 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
226 yield from ALUHelpers
.get_xer_so(res
, alu
, dec2
)
228 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
229 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
230 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
231 yield from ALUHelpers
.get_wr_sim_xer_ca(sim_o
, sim
, dec2
)
232 yield from ALUHelpers
.get_sim_xer_so(sim_o
, sim
, dec2
)
234 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
235 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
236 ALUHelpers
.check_xer_ca(self
, res
, sim_o
, code
)
237 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
238 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
241 if __name__
== "__main__":
242 unittest
.main(exit
=False)
243 suite
= unittest
.TestSuite()
244 suite
.addTest(TestRunner(MulTestCase
.test_data
))
246 runner
= unittest
.TextTestRunner()