src/soc/fu/mul/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
  16 from soc.fu.alu.alu_input_record import CompALUOpSubset
  17 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
  18 import random
  19
  20 class TestCase:
  21     def __init__(self, program, regs, sprs, name):
  22         self.program = program
  23         self.regs = regs
  24         self.sprs = sprs
  25         self.name = name
  26
  27 def get_rec_width(rec):
  28     recwidth = 0
  29     # Setup random inputs for dut.op
  30     for p in rec.ports():
  31         width = p.width
  32         recwidth += width
  33     return recwidth
  34
  35 def set_alu_inputs(alu, dec2, sim):
  36     inputs = []
  37     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  38     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  39     # and place it into data_i.b
  40
  41     reg3_ok = yield dec2.e.read_reg3.ok
  42     if reg3_ok:
  43         reg3_sel = yield dec2.e.read_reg3.data
  44         data3 = sim.gpr(reg3_sel).value
  45     else:
  46         data3 = 0
  47     reg1_ok = yield dec2.e.read_reg1.ok
  48     if reg1_ok:
  49         reg1_sel = yield dec2.e.read_reg1.data
  50         data1 = sim.gpr(reg1_sel).value
  51     else:
  52         data1 = 0
  53     reg2_ok = yield dec2.e.read_reg2.ok
  54     imm_ok = yield dec2.e.imm_data.ok
  55     if reg2_ok:
  56         reg2_sel = yield dec2.e.read_reg2.data
  57         data2 = sim.gpr(reg2_sel).value
  58     elif imm_ok:
  59         data2 = yield dec2.e.imm_data.imm
  60     else:
  61         data2 = 0
  62
  63     yield alu.p.data_i.ra.eq(data1)
  64     yield alu.p.data_i.rb.eq(data2)
  65     yield alu.p.data_i.rs.eq(data3)
  66
  67
  68 def set_extra_alu_inputs(alu, dec2, sim):
  69     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  70     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  71     yield alu.p.data_i.xer_ca[0].eq(carry)
  72     yield alu.p.data_i.xer_ca[1].eq(carry32)
  73     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  74     yield alu.p.data_i.xer_so.eq(so)
  75
  76
  77 # This test bench is a bit different than is usual. Initially when I
  78 # was writing it, I had all of the tests call a function to create a
  79 # device under test and simulator, initialize the dut, run the
  80 # simulation for ~2 cycles, and assert that the dut output what it
  81 # should have. However, this was really slow, since it needed to
  82 # create and tear down the dut and simulator for every test case.
  83
  84 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  85 # data into the test_data list below, describing the instructions to
  86 # be tested and the initial state. Once all the tests have been run,
  87 # test_data gets passed to TestRunner which then sets up the DUT and
  88 # simulator once, runs all the data through it, and asserts that the
  89 # results match the pseudocode sim at every cycle.
  90
  91 # By doing this, I've reduced the time it takes to run the test suite
  92 # massively. Before, it took around 1 minute on my computer, now it
  93 # takes around 3 seconds
  94
  95 test_data = []
  96
  97
  98 class ShiftRotTestCase(FHDLTestCase):
  99     def __init__(self, name):
 100         super().__init__(name)
 101         self.test_name = name
 102     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
 103         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
 104         test_data.append(tc)
 105
 106
 107     def test_shift(self):
 108         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
 109         for i in range(20):
 110             choice = random.choice(insns)
 111             lst = [f"{choice} 3, 1, 2"]
 112             initial_regs = [0] * 32
 113             initial_regs[1] = random.randint(0, (1<<64)-1)
 114             initial_regs[2] = random.randint(0, 63)
 115             print(initial_regs[1], initial_regs[2])
 116             self.run_tst_program(Program(lst), initial_regs)
 117
 118
 119     def test_shift_arith(self):
 120         lst = ["sraw 3, 1, 2"]
 121         initial_regs = [0] * 32
 122         initial_regs[1] = random.randint(0, (1<<64)-1)
 123         initial_regs[2] = random.randint(0, 63)
 124         print(initial_regs[1], initial_regs[2])
 125         self.run_tst_program(Program(lst), initial_regs)
 126
 127     def test_shift_once(self):
 128         lst = ["slw 3, 1, 4",
 129                "slw 3, 1, 2"]
 130         initial_regs = [0] * 32
 131         initial_regs[1] = 0x80000000
 132         initial_regs[2] = 0x40
 133         initial_regs[4] = 0x00
 134         self.run_tst_program(Program(lst), initial_regs)
 135
 136     def test_rlwinm(self):
 137         for i in range(10):
 138             mb = random.randint(0,31)
 139             me = random.randint(0,31)
 140             sh = random.randint(0,31)
 141             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}"]
 142             initial_regs = [0] * 32
 143             initial_regs[1] = random.randint(0, (1<<64)-1)
 144             self.run_tst_program(Program(lst), initial_regs)
 145
 146     def test_rlwimi(self):
 147         lst = ["rlwimi 3, 1, 5, 20, 6"]
 148         initial_regs = [0] * 32
 149         initial_regs[1] = 0xdeadbeef
 150         initial_regs[3] = 0x12345678
 151         self.run_tst_program(Program(lst), initial_regs)
 152
 153     def test_rlwnm(self):
 154         lst = ["rlwnm 3, 1, 2, 20, 6"]
 155         initial_regs = [0] * 32
 156         initial_regs[1] = random.randint(0, (1<<64)-1)
 157         initial_regs[2] = random.randint(0, 63)
 158         self.run_tst_program(Program(lst), initial_regs)
 159
 160     def test_rldicl(self):
 161         lst = ["rldicl 3, 1, 5, 20"]
 162         initial_regs = [0] * 32
 163         initial_regs[1] = random.randint(0, (1<<64)-1)
 164         self.run_tst_program(Program(lst), initial_regs)
 165
 166     def test_rldicr(self):
 167         lst = ["rldicr 3, 1, 5, 20"]
 168         initial_regs = [0] * 32
 169         initial_regs[1] = random.randint(0, (1<<64)-1)
 170         self.run_tst_program(Program(lst), initial_regs)
 171
 172     def test_rlc(self):
 173         insns = ["rldic", "rldicl", "rldicr"]
 174         for i in range(20):
 175             choice = random.choice(insns)
 176             sh = random.randint(0, 63)
 177             m = random.randint(0, 63)
 178             lst = [f"{choice} 3, 1, {sh}, {m}"]
 179             initial_regs = [0] * 32
 180             initial_regs[1] = random.randint(0, (1<<64)-1)
 181             self.run_tst_program(Program(lst), initial_regs)
 182
 183     def test_ilang(self):
 184         pspec = ShiftRotPipeSpec(id_wid=2)
 185         alu = ShiftRotBasePipe(pspec)
 186         vl = rtlil.convert(alu, ports=alu.ports())
 187         with open("pipeline.il", "w") as f:
 188             f.write(vl)
 189
 190
 191 class TestRunner(FHDLTestCase):
 192     def __init__(self, test_data):
 193         super().__init__("run_all")
 194         self.test_data = test_data
 195
 196     def run_all(self):
 197         m = Module()
 198         comb = m.d.comb
 199         instruction = Signal(32)
 200
 201         pdecode = create_pdecode()
 202
 203         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 204
 205         pspec = ShiftRotPipeSpec(id_wid=2)
 206         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 207
 208         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 209         comb += alu.p.valid_i.eq(1)
 210         comb += alu.n.ready_i.eq(1)
 211         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 212         sim = Simulator(m)
 213
 214         sim.add_clock(1e-6)
 215         def process():
 216             for test in self.test_data:
 217                 print(test.name)
 218                 program = test.program
 219                 self.subTest(test.name)
 220                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 221                 gen = program.generate_instructions()
 222                 instructions = list(zip(gen, program.assembly.splitlines()))
 223
 224                 index = simulator.pc.CIA.value//4
 225                 while index < len(instructions):
 226                     ins, code = instructions[index]
 227
 228                     print("0x{:X}".format(ins & 0xffffffff))
 229                     print(code)
 230
 231                     # ask the decoder to decode this binary data (endian'd)
 232                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 233                     yield instruction.eq(ins)          # raw binary instr.
 234                     yield Settle()
 235                     fn_unit = yield pdecode2.e.fn_unit
 236                     self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 237                     yield from set_alu_inputs(alu, pdecode2, simulator)
 238                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 239                     yield
 240                     opname = code.split(' ')[0]
 241                     yield from simulator.call(opname)
 242                     index = simulator.pc.CIA.value//4
 243
 244                     vld = yield alu.n.valid_o
 245                     while not vld:
 246                         yield
 247                         vld = yield alu.n.valid_o
 248                     yield
 249                     alu_out = yield alu.n.data_o.o
 250                     out_reg_valid = yield pdecode2.e.write_reg.ok
 251                     if out_reg_valid:
 252                         write_reg_idx = yield pdecode2.e.write_reg.data
 253                         expected = simulator.gpr(write_reg_idx).value
 254                         msg = f"expected {expected:x}, actual: {alu_out:x}"
 255                         self.assertEqual(expected, alu_out, msg)
 256                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 257                                                             simulator)
 258
 259         sim.add_sync_process(process)
 260         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 261                             traces=[]):
 262             sim.run()
 263     def check_extra_alu_outputs(self, alu, dec2, sim):
 264         rc = yield dec2.e.rc.data
 265         if rc:
 266             cr_expected = sim.crl[0].get_range().value
 267             cr_actual = yield alu.n.data_o.cr0
 268             self.assertEqual(cr_expected, cr_actual)
 269
 270
 271 if __name__ == "__main__":
 272     unittest.main(exit=False)
 273     suite = unittest.TestSuite()
 274     suite.addTest(TestRunner(test_data))
 275
 276     runner = unittest.TextTestRunner()
 277     runner.run(suite)