src/soc/fu/mul/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim.pysim import Simulator, Delay, Settle
   3 from nmigen.cli import rtlil
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller, special_sprs
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
   9 from soc.decoder.selectable_int import SelectableInt
  10 from soc.simulator.program import Program
  11 from soc.decoder.isa.all import ISA
  12 from soc.config.endian import bigendian
  13
  14 from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
  15 from soc.fu.mul.pipeline import MulBasePipe
  16 from soc.fu.mul.pipe_data import MulPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to MulFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  26     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  27     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  28
  29     print("alu get_cu_inputs", res)
  30
  31     return res
  32
  33
  34 def set_alu_inputs(alu, dec2, sim):
  35     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  36     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  37     # and place it into data_i.b
  38
  39     inp = yield from get_cu_inputs(dec2, sim)
  40     print("set alu inputs", inp)
  41     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  42     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  43
  44     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  45
  46
  47 # This test bench is a bit different than is usual. Initially when I
  48 # was writing it, I had all of the tests call a function to create a
  49 # device under test and simulator, initialize the dut, run the
  50 # simulation for ~2 cycles, and assert that the dut output what it
  51 # should have. However, this was really slow, since it needed to
  52 # create and tear down the dut and simulator for every test case.
  53
  54 # Now, instead of doing that, every test case in MulTestCase puts some
  55 # data into the test_data list below, describing the instructions to
  56 # be tested and the initial state. Once all the tests have been run,
  57 # test_data gets passed to TestRunner which then sets up the DUT and
  58 # simulator once, runs all the data through it, and asserts that the
  59 # results match the pseudocode sim at every cycle.
  60
  61 # By doing this, I've reduced the time it takes to run the test suite
  62 # massively. Before, it took around 1 minute on my computer, now it
  63 # takes around 3 seconds
  64
  65
  66 class MulTestCase(TestAccumulatorBase):
  67
  68     def case_0_mullw(self):
  69         lst = [f"mullw 3, 1, 2"]
  70         initial_regs = [0] * 32
  71         #initial_regs[1] = 0xffffffffffffffff
  72         #initial_regs[2] = 0xffffffffffffffff
  73         initial_regs[1] = 0x2ffffffff
  74         initial_regs[2] = 0x2
  75         self.add_case(Program(lst, bigendian), initial_regs)
  76
  77     def case_1_mullwo_(self):
  78         lst = [f"mullwo. 3, 1, 2"]
  79         initial_regs = [0] * 32
  80         initial_regs[1] = 0x3b34b06f
  81         initial_regs[2] = 0xfdeba998
  82         self.add_case(Program(lst, bigendian), initial_regs)
  83
  84     def case_2_mullwo(self):
  85         lst = [f"mullwo 3, 1, 2"]
  86         initial_regs = [0] * 32
  87         initial_regs[1] = 0xffffffffffffa988  # -5678
  88         initial_regs[2] = 0xffffffffffffedcc  # -1234
  89         self.add_case(Program(lst, bigendian), initial_regs)
  90
  91     def case_3_mullw(self):
  92         lst = ["mullw 3, 1, 2",
  93                "mullw 3, 1, 2"]
  94         initial_regs = [0] * 32
  95         initial_regs[1] = 0x6
  96         initial_regs[2] = 0xe
  97         self.add_case(Program(lst, bigendian), initial_regs)
  98
  99     def case_4_mullw_rand(self):
 100         for i in range(40):
 101             lst = ["mullw 3, 1, 2"]
 102             initial_regs = [0] * 32
 103             initial_regs[1] = random.randint(0, (1 << 64)-1)
 104             initial_regs[2] = random.randint(0, (1 << 64)-1)
 105             self.add_case(Program(lst, bigendian), initial_regs)
 106
 107     def case_4_mullw_nonrand(self):
 108         for i in range(40):
 109             lst = ["mullw 3, 1, 2"]
 110             initial_regs = [0] * 32
 111             initial_regs[1] = i+1
 112             initial_regs[2] = i+20
 113             self.add_case(Program(lst, bigendian), initial_regs)
 114
 115     def case_mulhw__regression_1(self):
 116         lst = ["mulhw. 3, 1, 2"
 117                ]
 118         initial_regs = [0] * 32
 119         initial_regs[1] = 0x7745b36eca6646fa
 120         initial_regs[2] = 0x47dfba3a63834ba2
 121         self.add_case(Program(lst, bigendian), initial_regs)
 122
 123     def case_rand_mul_lh(self):
 124         insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."]
 125         for i in range(40):
 126             choice = random.choice(insns)
 127             lst = [f"{choice} 3, 1, 2"]
 128             initial_regs = [0] * 32
 129             initial_regs[1] = random.randint(0, (1 << 64)-1)
 130             initial_regs[2] = random.randint(0, (1 << 64)-1)
 131             self.add_case(Program(lst, bigendian), initial_regs)
 132
 133     def case_rand_mullw(self):
 134         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
 135         for i in range(40):
 136             choice = random.choice(insns)
 137             lst = [f"{choice} 3, 1, 2"]
 138             initial_regs = [0] * 32
 139             initial_regs[1] = random.randint(0, (1 << 64)-1)
 140             initial_regs[2] = random.randint(0, (1 << 64)-1)
 141             self.add_case(Program(lst, bigendian), initial_regs)
 142
 143     def case_rand_mulld(self):
 144         insns = ["mulld", "mulld.", "mulldo", "mulldo."]
 145         for i in range(40):
 146             choice = random.choice(insns)
 147             lst = [f"{choice} 3, 1, 2"]
 148             initial_regs = [0] * 32
 149             initial_regs[1] = random.randint(0, (1 << 64)-1)
 150             initial_regs[2] = random.randint(0, (1 << 64)-1)
 151             self.add_case(Program(lst, bigendian), initial_regs)
 152
 153     def case_rand_mulhd(self):
 154         insns = ["mulhd", "mulhd."]
 155         for i in range(40):
 156             choice = random.choice(insns)
 157             lst = [f"{choice} 3, 1, 2"]
 158             initial_regs = [0] * 32
 159             initial_regs[1] = random.randint(0, (1 << 64)-1)
 160             initial_regs[2] = random.randint(0, (1 << 64)-1)
 161             self.add_case(Program(lst, bigendian), initial_regs)
 162
 163     def case_all(self):
 164         instrs = ["mulli","mulhw",
 165                   "mulhw.","mullw",
 166                   "mullw.","mullwo",
 167                   "mullwo.","mulhwu",
 168                   "mulhwu.","mulld",
 169                   "mulld.","mulldo",
 170                   "mulldo.","mulhd",
 171                   "mulhd.","mulhdu",
 172                   "mulhdu."]
 173
 174 # TODO add test case for these 3 operand cases
 175 # ,"maddhd","maddhdu","maddld"
 176
 177         test_values = [
 178             0x0,
 179             0x1,
 180             0x2,
 181             0xFFFF_FFFF_FFFF_FFFF,
 182             0xFFFF_FFFF_FFFF_FFFE,
 183             0x7FFF_FFFF_FFFF_FFFF,
 184             0x8000_0000_0000_0000,
 185             0x1234_5678_0000_0000,
 186             0x1234_5678_8000_0000,
 187             0x1234_5678_FFFF_FFFF,
 188             0x1234_5678_7FFF_FFFF,
 189             0xffffffff,
 190             0x7fffffff,
 191             0x80000000,
 192             0xfffffffe,
 193             0xfffffffd
 194         ]
 195
 196         for instr in instrs:
 197             l = [f"{instr} 3, 1, 2"]
 198             for ra in test_values:
 199                 for rb in test_values:
 200                     initial_regs = [0] * 32
 201                     initial_regs[1] = ra
 202                     initial_regs[2] = rb
 203                     # use "with" so as to close the files used
 204                     with Program(l, bigendian) as prog:
 205                         self.add_case(prog, initial_regs)
 206
 207     def case_all_rb_randint(self):
 208         instrs = ["mulli","mulhw",
 209                   "mulhw.","mullw",
 210                   "mullw.","mullwo",
 211                   "mullwo.","mulhwu",
 212                   "mulhwu.","mulld",
 213                   "mulld.","mulldo",
 214                   "mulldo.","mulhd",
 215                   "mulhd.","mulhdu",
 216                   "mulhdu."]
 217
 218         test_values = [
 219             0x0,
 220             0x1,
 221             0x2,
 222             0xFFFF_FFFF_FFFF_FFFF,
 223             0xFFFF_FFFF_FFFF_FFFE,
 224             0x7FFF_FFFF_FFFF_FFFF,
 225             0x8000_0000_0000_0000,
 226             0x1234_5678_0000_0000,
 227             0x1234_5678_8000_0000,
 228             0x1234_5678_FFFF_FFFF,
 229             0x1234_5678_7FFF_FFFF,
 230             0xffffffff,
 231             0x7fffffff,
 232             0x80000000,
 233             0xfffffffe,
 234             0xfffffffd
 235         ]
 236
 237         for instr in instrs:
 238             l = [f"{instr} 3, 1, 2"]
 239             for ra in test_values:
 240                 initial_regs = [0] * 32
 241                 initial_regs[1] = ra
 242                 initial_regs[2] = random.randint(0, (1 << 64)-1)
 243                 # use "with" so as to close the files used
 244                 with Program(l, bigendian) as prog:
 245                     self.add_case(prog, initial_regs)
 246
 247     def case_ilang(self):
 248         pspec = MulPipeSpec(id_wid=2)
 249         alu = MulBasePipe(pspec)
 250         vl = rtlil.convert(alu, ports=alu.ports())
 251         with open("mul_pipeline.il", "w") as f:
 252             f.write(vl)
 253
 254
 255 class TestRunner(unittest.TestCase):
 256     def __init__(self, test_data):
 257         super().__init__("run_all")
 258         self.test_data = test_data
 259
 260     def run_all(self):
 261         m = Module()
 262         comb = m.d.comb
 263         instruction = Signal(32)
 264
 265         pdecode = create_pdecode()
 266
 267         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 268
 269         pspec = MulPipeSpec(id_wid=2)
 270         m.submodules.alu = alu = MulBasePipe(pspec)
 271
 272         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 273         comb += alu.n.ready_i.eq(1)
 274         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 275         sim = Simulator(m)
 276
 277         sim.add_clock(1e-6)
 278
 279         def process():
 280             for test in self.test_data:
 281                 print(test.name)
 282                 program = test.program
 283                 self.subTest(test.name)
 284                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 285                           test.mem, test.msr,
 286                           bigendian=bigendian)
 287                 gen = program.generate_instructions()
 288                 instructions = list(zip(gen, program.assembly.splitlines()))
 289                 yield Settle()
 290
 291                 index = sim.pc.CIA.value//4
 292                 while index < len(instructions):
 293                     ins, code = instructions[index]
 294
 295                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 296                     print(code)
 297                     if 'XER' in sim.spr:
 298                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 299                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 300                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 301                         print("before: so/ov/32", so, ov, ov32)
 302
 303                     # ask the decoder to decode this binary data (endian'd)
 304                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
 305                     yield instruction.eq(ins)          # raw binary instr.
 306                     yield Settle()
 307                     fn_unit = yield pdecode2.e.do.fn_unit
 308                     self.assertEqual(fn_unit, Function.MUL.value)
 309                     yield from set_alu_inputs(alu, pdecode2, sim)
 310
 311                     # set valid for one cycle, propagate through pipeline...
 312                     yield alu.p.valid_i.eq(1)
 313                     yield
 314                     yield alu.p.valid_i.eq(0)
 315
 316                     opname = code.split(' ')[0]
 317                     yield from sim.call(opname)
 318                     index = sim.pc.CIA.value//4
 319
 320                     # ...wait for valid to pop out the end
 321                     vld = yield alu.n.valid_o
 322                     while not vld:
 323                         yield
 324                         vld = yield alu.n.valid_o
 325                     yield
 326
 327                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 328                     yield Settle()
 329
 330         sim.add_sync_process(process)
 331         with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
 332                            traces=[]):
 333             sim.run()
 334
 335     def check_alu_outputs(self, alu, dec2, sim, code):
 336
 337         rc = yield dec2.e.do.rc.data
 338         cridx_ok = yield dec2.e.write_cr.ok
 339         cridx = yield dec2.e.write_cr.data
 340
 341         print("check extra output", repr(code), cridx_ok, cridx)
 342         if rc:
 343             self.assertEqual(cridx, 0, code)
 344
 345         oe = yield dec2.e.do.oe.oe
 346         oe_ok = yield dec2.e.do.oe.ok
 347         if not oe or not oe_ok:
 348             # if OE not enabled, XER SO and OV must correspondingly be false
 349             so_ok = yield alu.n.data_o.xer_so.ok
 350             ov_ok = yield alu.n.data_o.xer_ov.ok
 351             self.assertEqual(so_ok, False, code)
 352             self.assertEqual(ov_ok, False, code)
 353
 354         sim_o = {}
 355         res = {}
 356
 357         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 358         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 359         yield from ALUHelpers.get_int_o(res, alu, dec2)
 360         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 361
 362         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 363         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 364         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 365         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 366
 367         ALUHelpers.check_int_o(self, res, sim_o, code)
 368         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 369         ALUHelpers.check_xer_so(self, res, sim_o, code)
 370         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 371
 372
 373 if __name__ == "__main__":
 374     unittest.main(exit=False)
 375     suite = unittest.TestSuite()
 376     suite.addTest(TestRunner(MulTestCase().test_data))
 377
 378     runner = unittest.TextTestRunner()
 379     runner.run(suite)