src/soc/fu/mul/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim.pysim import Simulator, Delay, Settle
   3 from nmigen.cli import rtlil
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller, special_sprs
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
   9 from soc.decoder.selectable_int import SelectableInt
  10 from soc.simulator.program import Program
  11 from soc.decoder.isa.all import ISA
  12 from soc.config.endian import bigendian
  13
  14 from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
  15 from soc.fu.mul.pipeline import MulBasePipe
  16 from soc.fu.mul.pipe_data import MulPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to MulFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  26     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  27     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  28
  29     print("alu get_cu_inputs", res)
  30
  31     return res
  32
  33
  34 def set_alu_inputs(alu, dec2, sim):
  35     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  36     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  37     # and place it into data_i.b
  38
  39     inp = yield from get_cu_inputs(dec2, sim)
  40     print("set alu inputs", inp)
  41     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  42     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  43
  44     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  45
  46
  47 # This test bench is a bit different than is usual. Initially when I
  48 # was writing it, I had all of the tests call a function to create a
  49 # device under test and simulator, initialize the dut, run the
  50 # simulation for ~2 cycles, and assert that the dut output what it
  51 # should have. However, this was really slow, since it needed to
  52 # create and tear down the dut and simulator for every test case.
  53
  54 # Now, instead of doing that, every test case in MulTestCase puts some
  55 # data into the test_data list below, describing the instructions to
  56 # be tested and the initial state. Once all the tests have been run,
  57 # test_data gets passed to TestRunner which then sets up the DUT and
  58 # simulator once, runs all the data through it, and asserts that the
  59 # results match the pseudocode sim at every cycle.
  60
  61 # By doing this, I've reduced the time it takes to run the test suite
  62 # massively. Before, it took around 1 minute on my computer, now it
  63 # takes around 3 seconds
  64
  65
  66 class MulTestCase(TestAccumulatorBase):
  67
  68     def case_0_mullw(self):
  69         lst = [f"mullw 3, 1, 2"]
  70         initial_regs = [0] * 32
  71         #initial_regs[1] = 0xffffffffffffffff
  72         #initial_regs[2] = 0xffffffffffffffff
  73         initial_regs[1] = 0x2ffffffff
  74         initial_regs[2] = 0x2
  75         self.add_case(Program(lst, bigendian), initial_regs)
  76
  77     def case_1_mullwo_(self):
  78         lst = [f"mullwo. 3, 1, 2"]
  79         initial_regs = [0] * 32
  80         initial_regs[1] = 0x3b34b06f
  81         initial_regs[2] = 0xfdeba998
  82         self.add_case(Program(lst, bigendian), initial_regs)
  83
  84     def case_2_mullwo(self):
  85         lst = [f"mullwo 3, 1, 2"]
  86         initial_regs = [0] * 32
  87         initial_regs[1] = 0xffffffffffffa988  # -5678
  88         initial_regs[2] = 0xffffffffffffedcc  # -1234
  89         self.add_case(Program(lst, bigendian), initial_regs)
  90
  91     def case_3_mullw(self):
  92         lst = ["mullw 3, 1, 2",
  93                "mullw 3, 1, 2"]
  94         initial_regs = [0] * 32
  95         initial_regs[1] = 0x6
  96         initial_regs[2] = 0xe
  97         self.add_case(Program(lst, bigendian), initial_regs)
  98
  99     def case_4_mullw_rand(self):
 100         for i in range(40):
 101             lst = ["mullw 3, 1, 2"]
 102             initial_regs = [0] * 32
 103             initial_regs[1] = random.randint(0, (1 << 64)-1)
 104             initial_regs[2] = random.randint(0, (1 << 64)-1)
 105             self.add_case(Program(lst, bigendian), initial_regs)
 106
 107     def case_4_mullw_nonrand(self):
 108         for i in range(40):
 109             lst = ["mullw 3, 1, 2"]
 110             initial_regs = [0] * 32
 111             initial_regs[1] = i+1
 112             initial_regs[2] = i+20
 113             self.add_case(Program(lst, bigendian), initial_regs)
 114
 115     def case_mulhw__regression_1(self):
 116         lst = ["mulhw. 3, 1, 2"
 117                ]
 118         initial_regs = [0] * 32
 119         initial_regs[1] = 0x7745b36eca6646fa
 120         initial_regs[2] = 0x47dfba3a63834ba2
 121         self.add_case(Program(lst, bigendian), initial_regs)
 122
 123     def case_rand_mul_lh(self):
 124         insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."]
 125         for i in range(40):
 126             choice = random.choice(insns)
 127             lst = [f"{choice} 3, 1, 2"]
 128             initial_regs = [0] * 32
 129             initial_regs[1] = random.randint(0, (1 << 64)-1)
 130             initial_regs[2] = random.randint(0, (1 << 64)-1)
 131             self.add_case(Program(lst, bigendian), initial_regs)
 132
 133     def case_rand_mullw(self):
 134         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
 135         for i in range(40):
 136             choice = random.choice(insns)
 137             lst = [f"{choice} 3, 1, 2"]
 138             initial_regs = [0] * 32
 139             initial_regs[1] = random.randint(0, (1 << 64)-1)
 140             initial_regs[2] = random.randint(0, (1 << 64)-1)
 141             self.add_case(Program(lst, bigendian), initial_regs)
 142
 143     def case_rand_mulld(self):
 144         insns = ["mulld", "mulld.", "mulldo", "mulldo."]
 145         for i in range(40):
 146             choice = random.choice(insns)
 147             lst = [f"{choice} 3, 1, 2"]
 148             initial_regs = [0] * 32
 149             initial_regs[1] = random.randint(0, (1 << 64)-1)
 150             initial_regs[2] = random.randint(0, (1 << 64)-1)
 151             self.add_case(Program(lst, bigendian), initial_regs)
 152
 153     def case_rand_mulhd(self):
 154         insns = ["mulhd", "mulhd."]
 155         for i in range(40):
 156             choice = random.choice(insns)
 157             lst = [f"{choice} 3, 1, 2"]
 158             initial_regs = [0] * 32
 159             initial_regs[1] = random.randint(0, (1 << 64)-1)
 160             initial_regs[2] = random.randint(0, (1 << 64)-1)
 161             self.add_case(Program(lst, bigendian), initial_regs)
 162
 163     def case_all(self):
 164         instrs = ["mulhw",
 165                   "mulhw.", "mullw",
 166                   "mullw.", "mullwo",
 167                   "mullwo.", "mulhwu",
 168                   "mulhwu.", "mulld",
 169                   "mulld.", "mulldo",
 170                   "mulldo.", "mulhd",
 171                   "mulhd.", "mulhdu",
 172                   "mulhdu."]
 173
 174         test_values = [
 175             0x0,
 176             0x1,
 177             0x2,
 178             0xFFFF_FFFF_FFFF_FFFF,
 179             0xFFFF_FFFF_FFFF_FFFE,
 180             0x7FFF_FFFF_FFFF_FFFF,
 181             0x8000_0000_0000_0000,
 182             0x1234_5678_0000_0000,
 183             0x1234_5678_8000_0000,
 184             0x1234_5678_FFFF_FFFF,
 185             0x1234_5678_7FFF_FFFF,
 186             0xffffffff,
 187             0x7fffffff,
 188             0x80000000,
 189             0xfffffffe,
 190             0xfffffffd
 191         ]
 192
 193         for instr in instrs:
 194             l = [f"{instr} 3, 1, 2"]
 195             for ra in test_values:
 196                 for rb in test_values:
 197                     initial_regs = [0] * 32
 198                     initial_regs[1] = ra
 199                     initial_regs[2] = rb
 200                     # use "with" so as to close the files used
 201                     with Program(l, bigendian) as prog:
 202                         self.add_case(prog, initial_regs)
 203
 204     def case_all_rb_randint(self):
 205         instrs = ["mulhw",
 206                   "mulhw.", "mullw",
 207                   "mullw.", "mullwo",
 208                   "mullwo.", "mulhwu",
 209                   "mulhwu.", "mulld",
 210                   "mulld.", "mulldo",
 211                   "mulldo.", "mulhd",
 212                   "mulhd.", "mulhdu",
 213                   "mulhdu."]
 214
 215         test_values = [
 216             0x0,
 217             0x1,
 218             0x2,
 219             0xFFFF_FFFF_FFFF_FFFF,
 220             0xFFFF_FFFF_FFFF_FFFE,
 221             0x7FFF_FFFF_FFFF_FFFF,
 222             0x8000_0000_0000_0000,
 223             0x1234_5678_0000_0000,
 224             0x1234_5678_8000_0000,
 225             0x1234_5678_FFFF_FFFF,
 226             0x1234_5678_7FFF_FFFF,
 227             0xffffffff,
 228             0x7fffffff,
 229             0x80000000,
 230             0xfffffffe,
 231             0xfffffffd
 232         ]
 233
 234         for instr in instrs:
 235             l = [f"{instr} 3, 1, 2"]
 236             for ra in test_values:
 237                 initial_regs = [0] * 32
 238                 initial_regs[1] = ra
 239                 initial_regs[2] = random.randint(0, (1 << 64)-1)
 240                 # use "with" so as to close the files used
 241                 with Program(l, bigendian) as prog:
 242                     self.add_case(prog, initial_regs)
 243
 244     def case_all_rb_close_to_ov(self):
 245         instrs = ["mulhw",
 246                   "mulhw.", "mullw",
 247                   "mullw.", "mullwo",
 248                   "mullwo.", "mulhwu",
 249                   "mulhwu.", "mulld",
 250                   "mulld.", "mulldo",
 251                   "mulldo.", "mulhd",
 252                   "mulhd.", "mulhdu",
 253                   "mulhdu."]
 254
 255         test_values = [
 256             0x0,
 257             0x1,
 258             0x2,
 259             0xFFFF_FFFF_FFFF_FFFF,
 260             0xFFFF_FFFF_FFFF_FFFE,
 261             0x7FFF_FFFF_FFFF_FFFF,
 262             0x8000_0000_0000_0000,
 263             0x1234_5678_0000_0000,
 264             0x1234_5678_8000_0000,
 265             0x1234_5678_FFFF_FFFF,
 266             0x1234_5678_7FFF_FFFF,
 267             0xffffffff,
 268             0x7fffffff,
 269             0x80000000,
 270             0xfffffffe,
 271             0xfffffffd
 272         ]
 273
 274         for instr in instrs:
 275             for i in range(20):
 276                 x = 0x7fffffff + random.randint(0, 1)
 277                 ra = random.randint(0, (1 << 32)-1)
 278                 rb = x // ra
 279
 280                 l = [f"{instr} 3, 1, 2"]
 281                 initial_regs = [0] * 32
 282                 initial_regs[1] = ra
 283                 initial_regs[2] = rb
 284                 # use "with" so as to close the files used
 285                 with Program(l, bigendian) as prog:
 286                     self.add_case(prog, initial_regs)
 287
 288     def case_mulli(self):
 289
 290         test_values = [-32768, -32767, -32766, -2, -1, 0, 1, 2, 32766, 32767, random.randint(-1 << 15, (1 << 15)-1), random.randint(-1 << 15, (
 291             1 << 15) - 1), random.randint(-1 << 15, (1 << 15)-1), random.randint(-1 << 15, (1 << 15)-1), random.randint(-1 << 15, (1 << 15)-1)]
 292
 293         l = ["mulli 3, 1, 2"]
 294         for ra in test_values:
 295             for rb in test_values:
 296                 initial_regs = [0] * 32
 297                 initial_regs[1] = ra
 298                 initial_regs[2] = rb
 299                 # use "with" so as to close the files used
 300                 with Program(l, bigendian) as prog:
 301                     self.add_case(prog, initial_regs)
 302
 303 # TODO add test case for these 3 operand cases (madd
 304 # needs to be implemented)
 305 # "maddhd","maddhdu","maddld"
 306
 307     def case_ilang(self):
 308         pspec = MulPipeSpec(id_wid=2)
 309         alu = MulBasePipe(pspec)
 310         vl = rtlil.convert(alu, ports=alu.ports())
 311         with open("mul_pipeline.il", "w") as f:
 312             f.write(vl)
 313
 314
 315 class TestRunner(unittest.TestCase):
 316     def __init__(self, test_data):
 317         super().__init__("run_all")
 318         self.test_data = test_data
 319
 320     def run_all(self):
 321         m = Module()
 322         comb = m.d.comb
 323         instruction = Signal(32)
 324
 325         pdecode = create_pdecode()
 326
 327         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 328
 329         pspec = MulPipeSpec(id_wid=2)
 330         m.submodules.alu = alu = MulBasePipe(pspec)
 331
 332         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 333         comb += alu.n.ready_i.eq(1)
 334         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 335         sim = Simulator(m)
 336
 337         sim.add_clock(1e-6)
 338
 339         def process():
 340             for test in self.test_data:
 341                 print(test.name)
 342                 program = test.program
 343                 self.subTest(test.name)
 344                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 345                           test.mem, test.msr,
 346                           bigendian=bigendian)
 347                 gen = program.generate_instructions()
 348                 instructions = list(zip(gen, program.assembly.splitlines()))
 349                 yield Settle()
 350
 351                 index = sim.pc.CIA.value//4
 352                 while index < len(instructions):
 353                     ins, code = instructions[index]
 354
 355                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 356                     print(code)
 357                     if 'XER' in sim.spr:
 358                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 359                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 360                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 361                         print("before: so/ov/32", so, ov, ov32)
 362
 363                     # ask the decoder to decode this binary data (endian'd)
 364                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
 365                     yield instruction.eq(ins)          # raw binary instr.
 366                     yield Settle()
 367                     fn_unit = yield pdecode2.e.do.fn_unit
 368                     self.assertEqual(fn_unit, Function.MUL.value)
 369                     yield from set_alu_inputs(alu, pdecode2, sim)
 370
 371                     # set valid for one cycle, propagate through pipeline...
 372                     yield alu.p.valid_i.eq(1)
 373                     yield
 374                     yield alu.p.valid_i.eq(0)
 375
 376                     opname = code.split(' ')[0]
 377                     yield from sim.call(opname)
 378                     index = sim.pc.CIA.value//4
 379
 380                     # ...wait for valid to pop out the end
 381                     vld = yield alu.n.valid_o
 382                     while not vld:
 383                         yield
 384                         vld = yield alu.n.valid_o
 385                     yield
 386
 387                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 388                     yield Settle()
 389
 390         sim.add_sync_process(process)
 391         with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
 392                            traces=[]):
 393             sim.run()
 394
 395     def check_alu_outputs(self, alu, dec2, sim, code):
 396
 397         rc = yield dec2.e.do.rc.data
 398         cridx_ok = yield dec2.e.write_cr.ok
 399         cridx = yield dec2.e.write_cr.data
 400
 401         print("check extra output", repr(code), cridx_ok, cridx)
 402         if rc:
 403             self.assertEqual(cridx, 0, code)
 404
 405         oe = yield dec2.e.do.oe.oe
 406         oe_ok = yield dec2.e.do.oe.ok
 407         if not oe or not oe_ok:
 408             # if OE not enabled, XER SO and OV must correspondingly be false
 409             so_ok = yield alu.n.data_o.xer_so.ok
 410             ov_ok = yield alu.n.data_o.xer_ov.ok
 411             self.assertEqual(so_ok, False, code)
 412             self.assertEqual(ov_ok, False, code)
 413
 414         sim_o = {}
 415         res = {}
 416
 417         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 418         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 419         yield from ALUHelpers.get_int_o(res, alu, dec2)
 420         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 421
 422         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 423         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 424         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 425         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 426
 427         ALUHelpers.check_int_o(self, res, sim_o, code)
 428         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 429         ALUHelpers.check_xer_so(self, res, sim_o, code)
 430         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 431
 432
 433 if __name__ == "__main__":
 434     unittest.main(exit=False)
 435     suite = unittest.TestSuite()
 436     suite.addTest(TestRunner(MulTestCase().test_data))
 437
 438     runner = unittest.TextTestRunner()
 439     runner.run(suite)