rename IntegerData to FUBaseData
[soc.git] / src / soc / fu / pipe_data.py
1 from nmutil.concurrentunit import PipeContext
2 from nmutil.dynamicpipe import SimpleHandshakeRedir
3 from nmigen import Signal
4 from openpower.decoder.power_decoder2 import Data
5 from soc.fu.regspec import get_regspec_bitwidth
6
7
8 class FUBaseData:
9 """FUBaseData: base class for all pipeline data structures
10
11 see README.md for explanation of parameters and purpose.
12
13 note the mode parameter - output. XXXInputData specs must
14 have this set to "False", and XXXOutputData specs (and anything
15 that creates intermediary outputs which propagate through a
16 pipeline *to* output) must have it set to "True".
17 """
18
19 def __init__(self, pspec, output):
20 self.ctx = PipeContext(pspec) # context for ReservationStation usage
21 self.muxid = self.ctx.muxid
22 self.data = []
23 self.is_output = output
24 for i, (regfile, regname, widspec) in enumerate(self.regspec):
25 wid = get_regspec_bitwidth([self.regspec], 0, i)
26 if output:
27 sig = Data(wid, name=regname)
28 else:
29 sig = Signal(wid, name=regname, reset_less=True)
30 setattr(self, regname, sig)
31 self.data.append(sig)
32
33 def __iter__(self):
34 yield from self.ctx
35 yield from self.data
36
37 def eq(self, i):
38 eqs = [self.ctx.eq(i.ctx)]
39 assert len(self.data) == len(i.data), \
40 "length of %s mismatch against %s: %s %s" % \
41 (repr(self), repr(i), repr(self.data), repr(i.data))
42 for j in range(len(self.data)):
43 assert type(self.data[j]) == type(i.data[j]), \
44 "type mismatch in FUBaseData %s %s" % \
45 (repr(self.data[j]), repr(i.data[j]))
46 eqs.append(self.data[j].eq(i.data[j]))
47 return eqs
48
49 def ports(self):
50 return self.ctx.ports() # TODO: include self.data
51
52
53 # hmmm there has to be a better way than this
54 def get_rec_width(rec):
55 recwidth = 0
56 # Setup random inputs for dut.op
57 for p in rec.ports():
58 width = p.width
59 recwidth += width
60 return recwidth
61
62
63 class CommonPipeSpec:
64 """CommonPipeSpec: base class for all pipeline specifications
65 see README.md for explanation of members.
66 """
67 def __init__(self, id_wid):
68 self.pipekls = SimpleHandshakeRedir
69 self.id_wid = id_wid
70 self.opkls = lambda _: self.opsubsetkls()
71 self.op_wid = get_rec_width(self.opkls(None)) # hmm..
72 self.stage = None