move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / pipe_data.py
1 from nmutil.concurrentunit import PipeContext
2 from nmutil.dynamicpipe import SimpleHandshakeRedir
3 from nmigen import Signal
4 from openpower.decoder.power_decoder2 import Data
5 from soc.fu.regspec import get_regspec_bitwidth
6
7
8 class FUBaseData:
9 """FUBaseData: base class for all pipeline data structures
10
11 see README.md for explanation of parameters and purpose.
12
13 note the mode parameter - output. XXXInputData specs must
14 have this set to "False", and XXXOutputData specs (and anything
15 that creates intermediary outputs which propagate through a
16 pipeline *to* output) must have it set to "True".
17 """
18
19 def __init__(self, pspec, output, exc_kls=None):
20 self.ctx = PipeContext(pspec) # context for ReservationStation usage
21 self.muxid = self.ctx.muxid
22 self.data = []
23 self.is_output = output
24 # take regspec and create data attributes (in or out)
25 # TODO: use widspec to create reduced bit mapping.
26 for i, (regfile, regname, widspec) in enumerate(self.regspec):
27 wid = get_regspec_bitwidth([self.regspec], 0, i)
28 if output:
29 sig = Data(wid, name=regname)
30 else:
31 sig = Signal(wid, name=regname, reset_less=True)
32 setattr(self, regname, sig)
33 self.data.append(sig)
34 # optional exception type
35 if exc_kls is not None:
36 name = "exc_o" if output else "exc_i"
37 self.exception = exc_kls(name=name)
38
39 def __iter__(self):
40 yield from self.ctx
41 yield from self.data
42 if hasattr(self, "exception"):
43 yield from self.exception.ports()
44
45 def eq(self, i):
46 eqs = [self.ctx.eq(i.ctx)]
47 assert len(self.data) == len(i.data), \
48 "length of %s mismatch against %s: %s %s" % \
49 (repr(self), repr(i), repr(self.data), repr(i.data))
50 for j in range(len(self.data)):
51 assert type(self.data[j]) == type(i.data[j]), \
52 "type mismatch in FUBaseData %s %s" % \
53 (repr(self.data[j]), repr(i.data[j]))
54 eqs.append(self.data[j].eq(i.data[j]))
55 if hasattr(self, "exception"):
56 eqs.append(self.exception.eq(i.exception))
57 return eqs
58
59 def ports(self):
60 return self.ctx.ports() # TODO: include self.data
61
62
63 # hmmm there has to be a better way than this
64 def get_rec_width(rec):
65 recwidth = 0
66 # Setup random inputs for dut.op
67 for p in rec.ports():
68 width = p.width
69 recwidth += width
70 return recwidth
71
72
73 class CommonPipeSpec:
74 """CommonPipeSpec: base class for all pipeline specifications
75 see README.md for explanation of members.
76 """
77 def __init__(self, id_wid):
78 self.pipekls = SimpleHandshakeRedir
79 self.id_wid = id_wid
80 self.opkls = lambda _: self.opsubsetkls()
81 self.op_wid = get_rec_width(self.opkls(None)) # hmm..
82 self.stage = None