src/soc/fu/pipe_data.py

   1 from ieee754.fpcommon.getop import FPPipeContext
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from nmigen import Signal
   4 from soc.decoder.power_decoder2 import Data
   5 from soc.fu.regspec import get_regspec_bitwidth
   6
   7 class IntegerData:
   8
   9     def __init__(self, pspec, output):
  10         self.ctx = FPPipeContext(pspec)
  11         self.muxid = self.ctx.muxid
  12         self.data = []
  13         self.is_output = output
  14         for i, (regfile, regname, widspec) in enumerate(self.regspec):
  15             wid = get_regspec_bitwidth([self.regspec], 0, i)
  16             if output:
  17                 sig = Data(wid, name=regname)
  18             else:
  19                 sig = Signal(wid, name=regname, reset_less=True)
  20             setattr(self, regname, sig)
  21             self.data.append(sig)
  22
  23     def __iter__(self):
  24         yield from self.ctx
  25         yield from self.data
  26
  27     def eq(self, i):
  28         eqs = [self.ctx.eq(i.ctx)]
  29         for j in range(len(self.data)):
  30             eqs.append(self.data[j].eq(i.data[j]))
  31         return eqs
  32
  33     def ports(self):
  34         return self.ctx.ports() # TODO: include self.data
  35
  36
  37 # hmmm there has to be a better way than this
  38 def get_rec_width(rec):
  39     recwidth = 0
  40     # Setup random inputs for dut.op
  41     for p in rec.ports():
  42         width = p.width
  43         recwidth += width
  44     return recwidth
  45
  46
  47 class CommonPipeSpec:
  48     def __init__(self, id_wid):
  49         self.pipekls = SimpleHandshakeRedir
  50         self.id_wid = id_wid
  51         self.opkls = lambda _: self.opsubsetkls(name="op")
  52         self.op_wid = get_rec_width(self.opkls(None)) # hmm..
  53         self.stage = None