move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / regspec.py
1 """RegSpecs
2
3 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
4
5 this module is a key strategic module that links pipeline specifications
6 (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits. MultiCompUnits
7 know absolutely nothing about the data passing through them: all they know
8 is: how many inputs they need to manage, and how many outputs.
9
10 regspecs tell MultiCompUnit what the ordering of the inputs is, how many to
11 create, and how to connect them up to the ALU being "managed" by this CompUnit.
12 likewise for outputs.
13
14 later (TODO) the Register Files will be connected to MultiCompUnits, and,
15 again, the regspecs will say which Regfile (which type) is connected to
16 which MultiCompUnit port, how wide the connection is, and so on.
17
18 """
19 from nmigen import Const
20 from soc.regfile.regfiles import XERRegs, FastRegs
21
22
23 def get_regspec_bitwidth(regspec, srcdest, idx):
24 print("get_regspec_bitwidth", regspec, srcdest, idx)
25 bitspec = regspec[srcdest][idx]
26 wid = 0
27 print(bitspec)
28 for ranges in bitspec[2].split(","):
29 ranges = ranges.split(":")
30 print(ranges)
31 if len(ranges) == 1: # only one bit
32 wid += 1
33 else:
34 start, end = map(int, ranges)
35 wid += (end-start)+1
36 return wid
37
38
39 class RegSpec:
40 def __init__(self, rwid, n_src=None, n_dst=None, name=None):
41 self._rwid = rwid
42 if isinstance(rwid, int):
43 # rwid: integer (covers all registers)
44 self._n_src, self._n_dst = n_src, n_dst
45 else:
46 # rwid: a regspec.
47 self._n_src, self._n_dst = len(rwid[0]), len(rwid[1])
48
49 def _get_dstwid(self, i):
50 if isinstance(self._rwid, int):
51 return self._rwid
52 return get_regspec_bitwidth(self._rwid, 1, i)
53
54 def _get_srcwid(self, i):
55 if isinstance(self._rwid, int):
56 return self._rwid
57 return get_regspec_bitwidth(self._rwid, 0, i)
58
59
60 class RegSpecAPI:
61 def __init__(self, rwid):
62 """RegSpecAPI
63
64 * :rwid: regspec
65 """
66 self.rwid = rwid
67
68 def get_in_spec(self, i):
69 return self.rwid[0][i]
70
71 def get_out_spec(self, i):
72 return self.rwid[1][i]
73
74 def get_in_name(self, i):
75 return self.get_in_spec(i)[1]
76
77 def get_out_name(self, i):
78 return self.get_out_spec(i)[1]
79
80
81 class RegSpecALUAPI(RegSpecAPI):
82 def __init__(self, rwid, alu):
83 """RegSpecAPI
84
85 * :rwid: regspec
86 * :alu: ALU covered by this regspec
87 """
88 super().__init__(rwid)
89 self.alu = alu
90
91 def get_out(self, i):
92 if isinstance(self.rwid, int): # old - testing - API (rwid is int)
93 return self.alu.out[i]
94 # regspec-based API: look up variable through regspec thru row number
95 return getattr(self.alu.n.data_o, self.get_out_name(i))
96
97 def get_in(self, i):
98 if isinstance(self.rwid, int): # old - testing - API (rwid is int)
99 return self.alu.i[i]
100 # regspec-based API: look up variable through regspec thru row number
101 return getattr(self.alu.p.data_i, self.get_in_name(i))
102
103 def get_op(self):
104 if isinstance(self.rwid, int): # old - testing - API (rwid is int)
105 return self.alu.op
106 return self.alu.p.data_i.ctx.op