src/soc/fu/regspec.py

   1 """RegSpecs
   2
   3 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
   4
   5 this module is a key strategic module that links pipeline specifications
   6 (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits.  MultiCompUnits
   7 know absolutely nothing about the data passing through them: all they know
   8 is: how many inputs they need to manage, and how many outputs.
   9
  10 regspecs tell MultiCompUnit what the ordering of the inputs is, how many to
  11 create, and how to connect them up to the ALU being "managed" by this CompUnit.
  12 likewise for outputs.
  13
  14 later (TODO) the Register Files will be connected to MultiCompUnits, and,
  15 again, the regspecs will say which Regfile (which type) is connected to
  16 which MultiCompUnit port, how wide the connection is, and so on.
  17
  18 """
  19 from nmigen import Const
  20 from soc.regfile.regfiles import XERRegs, FastRegs
  21
  22 def get_regspec_bitwidth(regspec, srcdest, idx):
  23     print ("get_regspec_bitwidth", regspec, srcdest, idx)
  24     bitspec = regspec[srcdest][idx]
  25     wid = 0
  26     print (bitspec)
  27     for ranges in bitspec[2].split(","):
  28         ranges = ranges.split(":")
  29         print (ranges)
  30         if len(ranges) == 1: # only one bit
  31             wid += 1
  32         else:
  33             start, end = map(int, ranges)
  34             wid += (end-start)+1
  35     return wid
  36
  37
  38 class RegSpec:
  39     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
  40         self._rwid = rwid
  41         if isinstance(rwid, int):
  42             # rwid: integer (covers all registers)
  43             self._n_src, self._n_dst = n_src, n_dst
  44         else:
  45             # rwid: a regspec.
  46             self._n_src, self._n_dst = len(rwid[0]), len(rwid[1])
  47
  48     def _get_dstwid(self, i):
  49         if isinstance(self._rwid, int):
  50             return self._rwid
  51         return get_regspec_bitwidth(self._rwid, 1, i)
  52
  53     def _get_srcwid(self, i):
  54         if isinstance(self._rwid, int):
  55             return self._rwid
  56         return get_regspec_bitwidth(self._rwid, 0, i)
  57
  58
  59 class RegSpecALUAPI:
  60     def __init__(self, rwid, alu):
  61         """RegSpecAPI
  62
  63         * :rwid:       regspec
  64         * :alu:        ALU covered by this regspec
  65         """
  66         self.rwid = rwid
  67         self.alu = alu # actual ALU - set as a "submodule" of the CU
  68
  69     def get_in_spec(self, i):
  70         return self.rwid[0][i]
  71
  72     def get_out_spec(self, i):
  73         return self.rwid[1][i]
  74
  75     def get_in_name(self, i):
  76         return self.get_in_spec(i)[1]
  77
  78     def get_out_name(self, i):
  79         return self.get_out_spec(i)[1]
  80
  81     def get_out(self, i):
  82         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  83             return self.alu.out[i]
  84         # regspec-based API: look up variable through regspec thru row number
  85         return getattr(self.alu.n.data_o, self.get_out_name(i))
  86
  87     def get_in(self, i):
  88         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  89             return self.alu.i[i]
  90         # regspec-based API: look up variable through regspec thru row number
  91         return getattr(self.alu.p.data_i, self.get_in_name(i))
  92
  93     def get_op(self):
  94         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  95             return self.alu.op
  96         return self.alu.p.data_i.ctx.op