src/soc/fu/regspec.py

   1 """RegSpecs
   2
   3 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
   4
   5 this module is a key strategic module that links pipeline specifications
   6 (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits.  MultiCompUnits
   7 know absolutely nothing about the data passing through them: all they know
   8 is: how many inputs they need to manage, and how many outputs.
   9
  10 regspecs tell MultiCompUnit what the ordering of the inputs is, how many to
  11 create, and how to connect them up to the ALU being "managed" by this CompUnit.
  12 likewise for outputs.
  13
  14 later (TODO) the Register Files will be connected to MultiCompUnits, and,
  15 again, the regspecs will say which Regfile (which type) is connected to
  16 which MultiCompUnit port, how wide the connection is, and so on.
  17
  18 """
  19 from nmigen import Const
  20 from soc.regfile.regfiles import XERRegs, FastRegs
  21
  22
  23 def get_regspec_bitwidth(regspec, srcdest, idx):
  24     print ("get_regspec_bitwidth", regspec, srcdest, idx)
  25     bitspec = regspec[srcdest][idx]
  26     wid = 0
  27     print (bitspec)
  28     for ranges in bitspec[2].split(","):
  29         ranges = ranges.split(":")
  30         print (ranges)
  31         if len(ranges) == 1: # only one bit
  32             wid += 1
  33         else:
  34             start, end = map(int, ranges)
  35             wid += (end-start)+1
  36     return wid
  37
  38
  39 class RegSpec:
  40     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
  41         self._rwid = rwid
  42         if isinstance(rwid, int):
  43             # rwid: integer (covers all registers)
  44             self._n_src, self._n_dst = n_src, n_dst
  45         else:
  46             # rwid: a regspec.
  47             self._n_src, self._n_dst = len(rwid[0]), len(rwid[1])
  48
  49     def _get_dstwid(self, i):
  50         if isinstance(self._rwid, int):
  51             return self._rwid
  52         return get_regspec_bitwidth(self._rwid, 1, i)
  53
  54     def _get_srcwid(self, i):
  55         if isinstance(self._rwid, int):
  56             return self._rwid
  57         return get_regspec_bitwidth(self._rwid, 0, i)
  58
  59
  60 class RegSpecALUAPI:
  61     def __init__(self, rwid, alu):
  62         """RegSpecAPI
  63
  64         * :rwid:       regspec
  65         * :alu:        ALU covered by this regspec
  66         """
  67         self.rwid = rwid
  68         self.alu = alu # actual ALU - set as a "submodule" of the CU
  69
  70     def get_in_spec(self, i):
  71         return self.rwid[0][i]
  72
  73     def get_out_spec(self, i):
  74         return self.rwid[1][i]
  75
  76     def get_in_name(self, i):
  77         return self.get_in_spec(i)[1]
  78
  79     def get_out_name(self, i):
  80         return self.get_out_spec(i)[1]
  81
  82     def get_out(self, i):
  83         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  84             return self.alu.out[i]
  85         # regspec-based API: look up variable through regspec thru row number
  86         return getattr(self.alu.n.data_o, self.get_out_name(i))
  87
  88     def get_in(self, i):
  89         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  90             return self.alu.i[i]
  91         # regspec-based API: look up variable through regspec thru row number
  92         return getattr(self.alu.p.data_i, self.get_in_name(i))
  93
  94     def get_op(self):
  95         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  96             return self.alu.op
  97         return self.alu.p.data_i.ctx.op