src/soc/fu/shift_rot/pipe_data.py

   1 from nmigen import Signal, Const, Cat
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   6 from soc.fu.logical.pipe_data import LogicalOutputData
   7 from nmutil.dynamicpipe import SimpleHandshakeRedir
   8
   9
  10 class ShiftRotInputData(IntegerData):
  11     regspec = [('INT', 'ra', '0:63'),
  12                ('INT', 'rb', '0:63'),
  13                ('INT', 'rc', '0:63'),
  14                ('XER', 'xer_ca', '34,45')]
  15     def __init__(self, pspec):
  16         super().__init__(pspec)
  17         self.ra = Signal(64, reset_less=True) # RA
  18         self.rb = Signal(64, reset_less=True) # RB
  19         self.rc = Signal(64, reset_less=True) # RS
  20         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  21         # convenience
  22         self.a, self.rs = self.ra, self.rc
  23
  24     def __iter__(self):
  25         yield from super().__iter__()
  26         yield self.ra
  27         yield self.rb
  28         yield self.rc
  29         yield self.xer_ca
  30
  31     def eq(self, i):
  32         lst = super().eq(i)
  33         return lst + [self.rc.eq(i.rc), self.ra.eq(i.ra),
  34                       self.rb.eq(i.rb),
  35                       self.xer_ca.eq(i.xer_ca) ]
  36
  37
  38 class ShiftRotPipeSpec(CommonPipeSpec):
  39     regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
  40     opsubsetkls = CompSROpSubset