1 from soc
.fu
.shift_rot
.sr_input_record
import CompSROpSubset
2 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
3 from soc
.fu
.logical
.pipe_data
import LogicalOutputData
6 class ShiftRotInputData(IntegerData
):
7 regspec
= [('INT', 'ra', '0:63'), # RA
8 ('INT', 'rb', '0:63'), # RB
9 ('INT', 'rc', '0:63'), # RS
10 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
11 def __init__(self
, pspec
):
12 super().__init
__(pspec
, False)
14 self
.a
, self
.rs
= self
.ra
, self
.rc
17 class ShiftRotPipeSpec(CommonPipeSpec
):
18 regspec
= (ShiftRotInputData
.regspec
, LogicalOutputData
.regspec
)
19 opsubsetkls
= CompSROpSubset