src/soc/fu/shift_rot/pipe_data.py

   1 from nmigen import Signal, Const
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from soc.fu.alu.alu_input_record import CompALUOpSubset
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.fu.pipe_data import IntegerData
   6 from soc.fu.alu.pipe_data import ALUOutputData
   7 from nmutil.dynamicpipe import SimpleHandshakeRedir
   8
   9
  10 class ShiftRotInputData(IntegerData):
  11     regspec = [('INT', 'ra', '0:63'),
  12                ('INT', 'rs', '0:63'),
  13                ('INT', 'rb', '0:63'),
  14                ('XER', 'xer_so', '32'),
  15                ('XER', 'xer_ca', '34,45')]
  16     def __init__(self, pspec):
  17         super().__init__(pspec)
  18         self.ra = Signal(64, reset_less=True) # RA
  19         self.rs = Signal(64, reset_less=True) # RS
  20         self.rb = Signal(64, reset_less=True) # RB/immediate
  21         self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
  22         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  23
  24     def __iter__(self):
  25         yield from super().__iter__()
  26         yield self.ra
  27         yield self.rs
  28         yield self.rb
  29         yield self.xer_ca
  30         yield self.xer_so
  31
  32     def eq(self, i):
  33         lst = super().eq(i)
  34         return lst + [self.rs.eq(i.rs), self.ra.eq(i.ra),
  35                       self.rb.eq(i.rb),
  36                       self.xer_ca.eq(i.xer_ca),
  37                       self.xer_so.eq(i.xer_so)]
  38
  39
  40 # TODO: replace CompALUOpSubset with CompShiftRotOpSubset
  41 class ShiftRotPipeSpec:
  42     regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec)
  43     opsubsetkls = CompALUOpSubset
  44     def __init__(self, id_wid, op_wid):
  45         self.id_wid = id_wid
  46         self.op_wid = op_wid
  47         self.opkls = lambda _: self.opsubsetkls(name="op")
  48         self.stage = None
  49         self.pipekls = SimpleHandshakeRedir