src/soc/fu/shift_rot/sr_input_record.py

   1 from nmigen.hdl.rec import Record, Layout
   2
   3 from soc.decoder.power_enums import InternalOp, Function, CryIn
   4
   5
   6 class CompSROpSubset(Record):
   7     """CompSROpSubset
   8
   9     a copy of the relevant subset information from Decode2Execute1Type
  10     needed for ALU operations.  use with eq_from_execute1 (below) to
  11     grab subsets.
  12     """
  13     def __init__(self, name=None):
  14         layout = (('insn_type', InternalOp),
  15                   ('fn_unit', Function),
  16                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
  17                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
  18                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
  19                   ('write_cr', Layout((("data", 3), ("ok", 1)))), # Data
  20                   ('input_carry', CryIn),
  21                   ('output_carry', 1),
  22                   ('input_cr', 1),
  23                   ('output_cr', 1),
  24                   ('is_32bit', 1),
  25                   ('is_signed', 1),
  26                   ('insn', 32),
  27                   )
  28
  29         Record.__init__(self, Layout(layout), name=name)
  30
  31         # grrr.  Record does not have kwargs
  32         self.insn_type.reset_less = True
  33         self.fn_unit.reset_less = True
  34         self.input_carry.reset_less = True
  35         self.output_carry.reset_less = True
  36         self.input_cr.reset_less = True
  37         self.output_cr.reset_less = True
  38         self.is_32bit.reset_less = True
  39         self.is_signed.reset_less = True
  40
  41     def eq_from_execute1(self, other):
  42         """ use this to copy in from Decode2Execute1Type
  43         """
  44         res = []
  45         for fname, sig in self.fields.items():
  46             eqfrom = other.fields[fname]
  47             res.append(sig.eq(eqfrom))
  48         return res
  49
  50     def ports(self):
  51         return [self.insn_type,
  52                 self.input_carry,
  53                 self.output_carry,
  54                 self.input_cr,
  55                 self.output_cr,
  56                 self.is_32bit,
  57                 self.is_signed,
  58         ]