src/soc/fu/shift_rot/test/test_maskgen.py

   1 from nmigen import Signal, Module
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 from soc.fu.shift_rot.maskgen import MaskGen
   6 from soc.decoder.helpers import MASK
   7 import random
   8 import unittest
   9
  10 class MaskGenTestCase(FHDLTestCase):
  11     def test_maskgen(self):
  12         m = Module()
  13         comb = m.d.comb
  14         m.submodules.dut = dut = MaskGen(64)
  15         mb = Signal.like(dut.mb)
  16         me = Signal.like(dut.me)
  17         o = Signal.like(dut.o)
  18
  19         comb += [
  20             dut.mb.eq(mb),
  21             dut.me.eq(me),
  22             o.eq(dut.o)]
  23
  24         sim = Simulator(m)
  25
  26         def process():
  27             for x in range(0, 64):
  28                 for y in range(0, 64):
  29                     yield mb.eq(x)
  30                     yield me.eq(y)
  31                     yield Delay(1e-6)
  32
  33                     expected = MASK(x, y)
  34                     result = yield o
  35                     self.assertEqual(expected, result)
  36
  37         sim.add_process(process) # or sim.add_sync_process(process), see below
  38         with sim.write_vcd("maskgen.vcd", "maskgen.gtkw", traces=dut.ports()):
  39             sim.run()
  40
  41     def test_ilang(self):
  42         dut = MaskGen(64)
  43         vl = rtlil.convert(dut, ports=dut.ports())
  44         with open("maskgen.il", "w") as f:
  45             f.write(vl)
  46
  47 if __name__ == '__main__':
  48     unittest.main()