src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Delay, Settle
   3 # NOTE: to use this (set to True), at present it is necessary to check
   4 # out the cxxsim nmigen branch
   5 cxxsim = False
   6 if cxxsim:
   7     try:
   8         from nmigen.sim.cxxsim import Simulator
   9     except ImportError:
  10         print("nope, sorry, have to use nmigen cxxsim branch for now")
  11         cxxsim = False
  12         from nmigen.back.pysim import Simulator
  13 else:
  14     from nmigen.back.pysim import Simulator
  15
  16 from nmutil.formaltest import FHDLTestCase
  17 from nmigen.cli import rtlil
  18 import unittest
  19 from soc.decoder.isa.caller import ISACaller, special_sprs
  20 from soc.decoder.power_decoder import (create_pdecode)
  21 from soc.decoder.power_decoder2 import (PowerDecode2)
  22 from soc.decoder.power_enums import (XER_bits, Function, CryIn)
  23 from soc.decoder.selectable_int import SelectableInt
  24 from soc.simulator.program import Program
  25 from soc.decoder.isa.all import ISA
  26 from soc.config.endian import bigendian
  27
  28 from soc.fu.test.common import TestCase, ALUHelpers
  29 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
  30 from soc.fu.alu.alu_input_record import CompALUOpSubset
  31 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
  32 import random
  33
  34
  35 def get_cu_inputs(dec2, sim):
  36     """naming (res) must conform to ShiftRotFunctionUnit input regspec
  37     """
  38     res = {}
  39
  40     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  41     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  42     yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC
  43     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  44
  45     print ("inputs", res)
  46
  47     return res
  48
  49
  50 def set_alu_inputs(alu, dec2, sim):
  51     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  52     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  53     # and place it into data_i.b
  54
  55     inp = yield from get_cu_inputs(dec2, sim)
  56     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  57     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  58     yield from ALUHelpers.set_int_rc(alu, dec2, inp)
  59     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  60
  61
  62 # This test bench is a bit different than is usual. Initially when I
  63 # was writing it, I had all of the tests call a function to create a
  64 # device under test and simulator, initialize the dut, run the
  65 # simulation for ~2 cycles, and assert that the dut output what it
  66 # should have. However, this was really slow, since it needed to
  67 # create and tear down the dut and simulator for every test case.
  68
  69 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  70 # data into the test_data list below, describing the instructions to
  71 # be tested and the initial state. Once all the tests have been run,
  72 # test_data gets passed to TestRunner which then sets up the DUT and
  73 # simulator once, runs all the data through it, and asserts that the
  74 # results match the pseudocode sim at every cycle.
  75
  76 # By doing this, I've reduced the time it takes to run the test suite
  77 # massively. Before, it took around 1 minute on my computer, now it
  78 # takes around 3 seconds
  79
  80
  81 class ShiftRotTestCase(FHDLTestCase):
  82     test_data = []
  83     def __init__(self, name):
  84         super().__init__(name)
  85         self.test_name = name
  86
  87     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  88         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  89         self.test_data.append(tc)
  90
  91     def test_shift(self):
  92         insns = ["slw", "sld", "srw", "srd", "sraw", "srad"]
  93         for i in range(20):
  94             choice = random.choice(insns)
  95             lst = [f"{choice} 3, 1, 2"]
  96             initial_regs = [0] * 32
  97             initial_regs[1] = random.randint(0, (1<<64)-1)
  98             initial_regs[2] = random.randint(0, 63)
  99             print(initial_regs[1], initial_regs[2])
 100             self.run_tst_program(Program(lst, bigendian), initial_regs)
 101
 102     def test_shift_arith(self):
 103         lst = ["sraw 3, 1, 2"]
 104         initial_regs = [0] * 32
 105         initial_regs[1] = random.randint(0, (1<<64)-1)
 106         initial_regs[2] = random.randint(0, 63)
 107         print(initial_regs[1], initial_regs[2])
 108         self.run_tst_program(Program(lst, bigendian), initial_regs)
 109
 110     def test_shift_once(self):
 111         lst = ["slw 3, 1, 4",
 112                "slw 3, 1, 2"]
 113         initial_regs = [0] * 32
 114         initial_regs[1] = 0x80000000
 115         initial_regs[2] = 0x40
 116         initial_regs[4] = 0x00
 117         self.run_tst_program(Program(lst, bigendian), initial_regs)
 118
 119     def test_rlwinm(self):
 120         for i in range(10):
 121             mb = random.randint(0,31)
 122             me = random.randint(0,31)
 123             sh = random.randint(0,31)
 124             lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}",
 125                    #f"rlwinm. 3, 1, {mb}, {me}, {sh}"
 126                    ]
 127             initial_regs = [0] * 32
 128             initial_regs[1] = random.randint(0, (1<<64)-1)
 129             self.run_tst_program(Program(lst, bigendian), initial_regs)
 130
 131     def test_rlwimi(self):
 132         lst = ["rlwimi 3, 1, 5, 20, 6"]
 133         initial_regs = [0] * 32
 134         initial_regs[1] = 0xdeadbeef
 135         initial_regs[3] = 0x12345678
 136         self.run_tst_program(Program(lst, bigendian), initial_regs)
 137
 138     def test_rlwnm(self):
 139         lst = ["rlwnm 3, 1, 2, 20, 6"]
 140         initial_regs = [0] * 32
 141         initial_regs[1] = random.randint(0, (1<<64)-1)
 142         initial_regs[2] = random.randint(0, 63)
 143         self.run_tst_program(Program(lst, bigendian), initial_regs)
 144
 145     def test_rldicl(self):
 146         lst = ["rldicl 3, 1, 5, 20"]
 147         initial_regs = [0] * 32
 148         initial_regs[1] = random.randint(0, (1<<64)-1)
 149         self.run_tst_program(Program(lst, bigendian), initial_regs)
 150
 151     def test_rldicr(self):
 152         lst = ["rldicr 3, 1, 5, 20"]
 153         initial_regs = [0] * 32
 154         initial_regs[1] = random.randint(0, (1<<64)-1)
 155         self.run_tst_program(Program(lst, bigendian), initial_regs)
 156
 157     def test_regression_extswsli(self):
 158         lst = [f"extswsli 3, 1, 34"]
 159         initial_regs = [0] * 32
 160         initial_regs[1] = 0x5678
 161         self.run_tst_program(Program(lst, bigendian), initial_regs)
 162
 163     def test_regression_extswsli_2(self):
 164         lst = [f"extswsli 3, 1, 7"]
 165         initial_regs = [0] * 32
 166         initial_regs[1] = 0x3ffffd7377f19fdd
 167         self.run_tst_program(Program(lst, bigendian), initial_regs)
 168
 169     def test_regression_extswsli_3(self):
 170         lst = [f"extswsli 3, 1, 0"]
 171         initial_regs = [0] * 32
 172         #initial_regs[1] = 0x80000000fb4013e2
 173         #initial_regs[1] = 0xffffffffffffffff
 174         #initial_regs[1] = 0x00000000ffffffff
 175         initial_regs[1] = 0x0000010180122900
 176         #initial_regs[1] = 0x3ffffd73f7f19fdd
 177         self.run_tst_program(Program(lst, bigendian), initial_regs)
 178
 179     def test_extswsli(self):
 180         for i in range(40):
 181             sh = random.randint(0, 63)
 182             lst = [f"extswsli 3, 1, {sh}"]
 183             initial_regs = [0] * 32
 184             initial_regs[1] = random.randint(0, (1<<64)-1)
 185             self.run_tst_program(Program(lst, bigendian), initial_regs)
 186
 187     def test_rlc(self):
 188         insns = ["rldic", "rldicl", "rldicr"]
 189         for i in range(20):
 190             choice = random.choice(insns)
 191             sh = random.randint(0, 63)
 192             m = random.randint(0, 63)
 193             lst = [f"{choice} 3, 1, {sh}, {m}"]
 194             initial_regs = [0] * 32
 195             initial_regs[1] = random.randint(0, (1<<64)-1)
 196             self.run_tst_program(Program(lst, bigendian), initial_regs)
 197
 198     def test_ilang(self):
 199         pspec = ShiftRotPipeSpec(id_wid=2)
 200         alu = ShiftRotBasePipe(pspec)
 201         vl = rtlil.convert(alu, ports=alu.ports())
 202         with open("pipeline.il", "w") as f:
 203             f.write(vl)
 204
 205
 206 class TestRunner(FHDLTestCase):
 207     def __init__(self, test_data):
 208         super().__init__("run_all")
 209         self.test_data = test_data
 210
 211     def run_all(self):
 212         m = Module()
 213         comb = m.d.comb
 214         instruction = Signal(32)
 215
 216         pdecode = create_pdecode()
 217
 218         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 219
 220         pspec = ShiftRotPipeSpec(id_wid=2)
 221         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 222
 223         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 224         comb += alu.p.valid_i.eq(1)
 225         comb += alu.n.ready_i.eq(1)
 226         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 227         sim = Simulator(m)
 228
 229         sim.add_clock(1e-6)
 230         def process():
 231             for test in self.test_data:
 232                 print(test.name)
 233                 program = test.program
 234                 self.subTest(test.name)
 235                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
 236                                 test.mem, test.msr,
 237                                 bigendian=bigendian)
 238                 gen = program.generate_instructions()
 239                 instructions = list(zip(gen, program.assembly.splitlines()))
 240
 241                 index = simulator.pc.CIA.value//4
 242                 while index < len(instructions):
 243                     ins, code = instructions[index]
 244
 245                     print("0x{:X}".format(ins & 0xffffffff))
 246                     print(code)
 247
 248                     # ask the decoder to decode this binary data (endian'd)
 249                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
 250                     yield instruction.eq(ins)          # raw binary instr.
 251                     yield Settle()
 252                     fn_unit = yield pdecode2.e.do.fn_unit
 253                     self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 254                     yield from set_alu_inputs(alu, pdecode2, simulator)
 255                     yield
 256                     opname = code.split(' ')[0]
 257                     yield from simulator.call(opname)
 258                     index = simulator.pc.CIA.value//4
 259
 260                     vld = yield alu.n.valid_o
 261                     while not vld:
 262                         yield
 263                         vld = yield alu.n.valid_o
 264                     yield
 265                     alu_out = yield alu.n.data_o.o.data
 266
 267                     yield from self.check_alu_outputs(alu, pdecode2,
 268                                                             simulator, code)
 269                     break
 270
 271         sim.add_sync_process(process)
 272         print (dir(sim))
 273         if cxxsim:
 274             sim.run()
 275         else:
 276             with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 277                                 traces=[]):
 278                 sim.run()
 279
 280     def check_alu_outputs(self, alu, dec2, sim, code):
 281
 282         rc = yield dec2.e.do.rc.data
 283         cridx_ok = yield dec2.e.write_cr.ok
 284         cridx = yield dec2.e.write_cr.data
 285
 286         print ("check extra output", repr(code), cridx_ok, cridx)
 287         if rc:
 288             self.assertEqual(cridx, 0, code)
 289
 290         sim_o = {}
 291         res = {}
 292
 293         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 294         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 295         yield from ALUHelpers.get_int_o(res, alu, dec2)
 296
 297         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 298         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 299         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 300
 301         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 302         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 303         ALUHelpers.check_int_o(self, res, sim_o, code)
 304
 305
 306
 307 if __name__ == "__main__":
 308     unittest.main(exit=False)
 309     suite = unittest.TestSuite()
 310     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 311
 312     runner = unittest.TextTestRunner()
 313     runner.run(suite)