src/soc/fu/shift_rot/test/test_pipe_caller.py

   1 import random
   2 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
   3 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
   4 from openpower.test.common import TestAccumulatorBase, TestCase, ALUHelpers
   5 from openpower.endian import bigendian
   6 from openpower.decoder.isa.all import ISA
   7 from openpower.simulator.program import Program
   8 from openpower.decoder.power_enums import (XER_bits, Function, CryIn)
   9 from openpower.decoder.power_decoder2 import (PowerDecode2)
  10 from openpower.decoder.power_decoder import (create_pdecode)
  11 import unittest
  12 from nmigen.cli import rtlil
  13 from nmigen import Module, Signal
  14
  15 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  16 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  17 from nmutil.sim_tmp_alternative import Simulator, Settle
  18
  19 from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase
  20 from openpower.test.bitmanip.bitmanip_cases import BitManipTestCase
  21
  22
  23 def get_cu_inputs(dec2, sim):
  24     """naming (res) must conform to ShiftRotFunctionUnit input regspec
  25     """
  26     res = {}
  27
  28     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  29     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  30     yield from ALUHelpers.get_sim_int_rc(res, sim, dec2)  # RC
  31     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2)  # XER.ca
  32     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  33
  34     print("alu get_cu_inputs", res)
  35
  36     return res
  37
  38
  39 def set_alu_inputs(alu, dec2, sim):
  40     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  41     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  42     # and place it into i_data.b
  43
  44     inp = yield from get_cu_inputs(dec2, sim)
  45     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  46     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  47     yield from ALUHelpers.set_int_rc(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  49     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  50
  51
  52 # This test bench is a bit different than is usual. Initially when I
  53 # was writing it, I had all of the tests call a function to create a
  54 # device under test and simulator, initialize the dut, run the
  55 # simulation for ~2 cycles, and assert that the dut output what it
  56 # should have. However, this was really slow, since it needed to
  57 # create and tear down the dut and simulator for every test case.
  58
  59 # Now, instead of doing that, every test case in ShiftRotTestCase puts some
  60 # data into the test_data list below, describing the instructions to
  61 # be tested and the initial state. Once all the tests have been run,
  62 # test_data gets passed to TestRunner which then sets up the DUT and
  63 # simulator once, runs all the data through it, and asserts that the
  64 # results match the pseudocode sim at every cycle.
  65
  66 # By doing this, I've reduced the time it takes to run the test suite
  67 # massively. Before, it took around 1 minute on my computer, now it
  68 # takes around 3 seconds
  69
  70
  71 class ShiftRotIlangCase(TestAccumulatorBase):
  72
  73     def case_ilang(self):
  74         class PPspec:
  75             XLEN = 64
  76         pps = PPspec()
  77         pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=pps)
  78         pspec.draft_bitmanip = True
  79         alu = ShiftRotBasePipe(pspec)
  80         vl = rtlil.convert(alu, ports=alu.ports())
  81         with open("shift_rot_pipeline.il", "w") as f:
  82             f.write(vl)
  83
  84
  85 class TestRunner(unittest.TestCase):
  86     def __init__(self, test_data):
  87         super().__init__("run_all")
  88         self.test_data = test_data
  89
  90     def execute(self, alu, instruction, pdecode2, test):
  91         program = test.program
  92         simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
  93                         test.mem, test.msr,
  94                         bigendian=bigendian)
  95         gen = program.generate_instructions()
  96         instructions = list(zip(gen, program.assembly.splitlines()))
  97
  98         index = simulator.pc.CIA.value//4
  99         while index < len(instructions):
 100             ins, code = instructions[index]
 101
 102             print("0x{:X}".format(ins & 0xffffffff))
 103             print(code)
 104
 105             # ask the decoder to decode this binary data (endian'd)
 106             yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
 107             yield instruction.eq(ins)          # raw binary instr.
 108             yield Settle()
 109             fn_unit = yield pdecode2.e.do.fn_unit
 110             self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
 111             yield from set_alu_inputs(alu, pdecode2, simulator)
 112
 113             # set valid for one cycle, propagate through pipeline...
 114             yield alu.p.i_valid.eq(1)
 115             yield
 116             yield alu.p.i_valid.eq(0)
 117
 118             opname = code.split(' ')[0]
 119             yield from simulator.call(opname)
 120             index = simulator.pc.CIA.value//4
 121
 122             vld = yield alu.n.o_valid
 123             while not vld:
 124                 yield
 125                 vld = yield alu.n.o_valid
 126             yield
 127             alu_out = yield alu.n.o_data.o.data
 128
 129             yield from self.check_alu_outputs(alu, pdecode2,
 130                                               simulator, code)
 131             yield Settle()
 132
 133     def run_all(self):
 134         m = Module()
 135         comb = m.d.comb
 136         instruction = Signal(32)
 137
 138         fn_name = "SHIFT_ROT"
 139         opkls = ShiftRotPipeSpec.opsubsetkls
 140
 141         m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
 142         pdecode = pdecode2.dec
 143
 144         class PPspec:
 145             XLEN = 64
 146         pps = PPspec()
 147         pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=pps)
 148         pspec.draft_bitmanip = True
 149         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 150
 151         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
 152         comb += alu.n.i_ready.eq(1)
 153         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 154         sim = Simulator(m)
 155
 156         sim.add_clock(1e-6)
 157
 158         def process():
 159             for test in self.test_data:
 160                 print(test.name)
 161                 program = test.program
 162                 with self.subTest(test.name):
 163                     yield from self.execute(alu, instruction, pdecode2, test)
 164
 165         sim.add_sync_process(process)
 166         with sim.write_vcd("shift_rot_simulator.vcd"):
 167             sim.run()
 168
 169     def check_alu_outputs(self, alu, dec2, sim, code):
 170
 171         rc = yield dec2.e.do.rc.rc
 172         cridx_ok = yield dec2.e.write_cr.ok
 173         cridx = yield dec2.e.write_cr.data
 174
 175         print("check extra output", repr(code), cridx_ok, cridx)
 176         if rc:
 177             self.assertEqual(cridx, 0, code)
 178
 179         sim_o = {}
 180         res = {}
 181
 182         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 183         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 184         yield from ALUHelpers.get_int_o(res, alu, dec2)
 185
 186         print("hw outputs", res)
 187
 188         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 189         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 190         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 191
 192         print("sim outputs", sim_o)
 193
 194         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 195         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 196         ALUHelpers.check_int_o(self, res, sim_o, code)
 197
 198
 199 if __name__ == "__main__":
 200     unittest.main(exit=False)
 201     suite = unittest.TestSuite()
 202     suite.addTest(TestRunner(ShiftRotTestCase().test_data))
 203     suite.addTest(TestRunner(BitManipTestCase().test_data))
 204     suite.addTest(TestRunner(ShiftRotIlangCase().test_data))
 205
 206     runner = unittest.TextTestRunner()
 207     runner.run(suite)