007610af42901ee58732ce76dfe30e54af413df8
1 """SPR Pipeline Data structures
3 Covers MFSPR and MTSPR. however given that the SPRs are split across
4 XER (which is 3 separate registers), Fast-SPR and Slow-SPR regfiles,
5 the data structures are slightly more involved than just "INT, SPR".
8 * https://bugs.libre-soc.org/show_bug.cgi?id=348
9 * https://libre-soc.org/openpower/isa/sprset/
12 from nmigen
import Signal
, Const
13 from ieee754
.fpcommon
.getop
import FPPipeContext
14 from soc
.fu
.pipe_data
import IntegerData
15 from soc
.decoder
.power_decoder2
import Data
16 from soc
.fu
.spr
.spr_input_record
import CompSPROpSubset
19 class SPRInputData(IntegerData
):
20 regspec
= [('INT', 'ra', '0:63'), # RA
21 ('SPR', 'spr1', '0:63'), # SPR (slow)
22 ('FAST', 'spr2', '0:63'), # SPR (fast: MSR, LR, CTR etc)
23 ('XER', 'xer_so', '32'), # XER bit 32: SO
24 ('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
25 ('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
26 def __init__(self
, pspec
):
27 super().__init
__(pspec
, False)
32 class SPROutputData(IntegerData
):
33 regspec
= [('INT', 'o', '0:63'), # RT
34 ('SPR', 'spr1', '0:63'), # SPR (slow)
35 ('FAST', 'spr2', '0:63'), # SPR (fast: MSR, LR, CTR etc)
36 ('XER', 'xer_so', '32'), # XER bit 32: SO
37 ('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
38 ('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
39 def __init__(self
, pspec
):
40 super().__init
__(pspec
, True)
44 regspec
= (SPRInputData
.regspec
, SPROutputData
.regspec
)
45 opsubsetkls
= CompSPROpSubset
46 def __init__(self
, id_wid
, op_wid
):
49 self
.opkls
= lambda _
: self
.opsubsetkls(name
="op")
51 self
.pipekls
= SimpleHandshakeRedir