remove unneeded imports
[soc.git] / src / soc / fu / spr / pipe_data.py
1 """SPR Pipeline Data structures
2
3 Covers MFSPR and MTSPR. however given that the SPRs are split across
4 XER (which is 3 separate registers), Fast-SPR and Slow-SPR regfiles,
5 the data structures are slightly more involved than just "INT, SPR".
6
7 Links:
8 * https://bugs.libre-soc.org/show_bug.cgi?id=348
9 * https://libre-soc.org/openpower/isa/sprset/
10 """
11
12 from soc.fu.pipe_data import IntegerData
13 from soc.fu.spr.spr_input_record import CompSPROpSubset
14
15
16 class SPRInputData(IntegerData):
17 regspec = [('INT', 'ra', '0:63'), # RA
18 ('SPR', 'spr1', '0:63'), # SPR (slow)
19 ('FAST', 'spr2', '0:63'), # SPR (fast: MSR, LR, CTR etc)
20 ('XER', 'xer_so', '32'), # XER bit 32: SO
21 ('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
22 ('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
23 def __init__(self, pspec):
24 super().__init__(pspec, False)
25 # convenience
26 self.a = self.ra
27
28
29 class SPROutputData(IntegerData):
30 regspec = [('INT', 'o', '0:63'), # RT
31 ('SPR', 'spr1', '0:63'), # SPR (slow)
32 ('FAST', 'spr2', '0:63'), # SPR (fast: MSR, LR, CTR etc)
33 ('XER', 'xer_so', '32'), # XER bit 32: SO
34 ('XER', 'xer_ov', '33,44'), # XER bit 34/45: CA/CA32
35 ('XER', 'xer_ca', '34,45')] # bit0: ov, bit1: ov32
36 def __init__(self, pspec):
37 super().__init__(pspec, True)
38
39
40 class SPRPipeSpec:
41 regspec = (SPRInputData.regspec, SPROutputData.regspec)
42 opsubsetkls = CompSPROpSubset