src/soc/fu/spr/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5 from soc.fu.spr.spr_input_record import CompSPROpSubset
   6
   7
   8 class SPRInputData(IntegerData):
   9     regspec = [('INT', 'a', '0:63'),
  10                ('SPR', 'spr1', '0:63'),
  11                ('FAST', 'spr2', '0:63'),
  12                ('XER', 'xer_so', '32'),
  13                ('XER', 'xer_ov', '33,44'),
  14                ('XER', 'xer_ca', '34,45')]
  15     def __init__(self, pspec):
  16         super().__init__(pspec)
  17         self.a = Signal(64, reset_less=True) # RA
  18         self.spr1 = Signal(64, reset_less=True) # SPR (slow)
  19         self.spr2 = Signal(64, reset_less=True) # SPR (fast: MSR, LR, CTR etc)
  20         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
  21         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  22         self.xer_ov = Signal(2, reset_less=True) # bit0: ov, bit1: ov32
  23
  24     def __iter__(self):
  25         yield from super().__iter__()
  26         yield self.a
  27         yield self.spr1
  28         yield self.spr2
  29         yield self.xer_ca
  30         yield self.xer_ov
  31         yield self.xer_so
  32
  33     def eq(self, i):
  34         lst = super().eq(i)
  35         return lst + [self.a.eq(i.a), self.reg.eq(i.reg),
  36                       self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  37                       self.xer_ca.eq(i.xer_ca),
  38                       self.xer_ov.eq(i.xer_ov),
  39                       self.xer_so.eq(i.xer_so)]
  40
  41
  42 class SPROutputData(IntegerData):
  43     regspec = [('INT', 'o', '0:63'),
  44                ('SPR', 'spr1', '0:63'),
  45                ('FAST', 'spr2', '0:63'),
  46                ('XER', 'xer_so', '32'),
  47                ('XER', 'xer_ov', '33,44'),
  48                ('XER', 'xer_ca', '34,45')]
  49     def __init__(self, pspec):
  50         super().__init__(pspec)
  51         self.o = Data(64, name="rt") # RT
  52         self.spr1 = Data(64, name="spr1") # SPR (slow)
  53         self.spr2 = Data(64, name="spr2") # SPR (fast: MSR, LR, CTR etc)
  54         self.xer_so = Data(1, name="xer_so") # XER bit 32: SO
  55         self.xer_ca = Data(2, name="xer_ca") # XER bit 34/45: CA/CA32
  56         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
  57
  58     def __iter__(self):
  59         yield from super().__iter__()
  60         yield self.o
  61         yield self.spr1
  62         yield self.spr2
  63         yield self.xer_ca
  64         yield self.xer_ov
  65         yield self.xer_so
  66
  67     def eq(self, i):
  68         lst = super().eq(i)
  69         return lst + [self.o.eq(i.o), self.reg.eq(i.reg),
  70                       self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  71                       self.xer_ca.eq(i.xer_ca),
  72                       self.xer_ov.eq(i.xer_ov),
  73                       self.xer_so.eq(i.xer_so)]
  74
  75
  76
  77 class SPRPipeSpec:
  78     regspec = (SPRInputData.regspec, SPROutputData.regspec)
  79     opsubsetkls = CompSPROpSubset
  80     def __init__(self, id_wid, op_wid):
  81         self.id_wid = id_wid
  82         self.op_wid = op_wid
  83         self.opkls = lambda _: self.opsubsetkls(name="op")
  84         self.stage = None
  85         self.pipekls = SimpleHandshakeRedir