big reorg on PowerDecoder2, actually Decode2Execute1Type
[soc.git] / src / soc / fu / spr / spr_input_record.py
1 from nmigen.hdl.rec import Record, Layout
2
3 from soc.decoder.power_enums import (InternalOp, Function)
4
5
6 class CompSPROpSubset(Record):
7 """CompSPROpSubset
8
9 a copy of the relevant subset information from Decode2Execute1Type
10 needed for TRAP operations. use with eq_from_execute1 (below) to
11 grab subsets.
12 """
13 def __init__(self, name=None):
14 layout = (('insn_type', InternalOp),
15 ('fn_unit', Function),
16 ('insn', 32),
17 ('is_32bit', 1),
18 )
19
20 Record.__init__(self, Layout(layout), name=name)
21
22 # grrr. Record does not have kwargs
23 self.insn_type.reset_less = True
24 self.insn.reset_less = True
25 self.fn_unit.reset_less = True
26 self.is_32bit.reset_less = True
27
28 def eq_from_execute1(self, other):
29 """ use this to copy in from Decode2Execute1Type
30 """
31 res = []
32 for fname, sig in self.fields.items():
33 eqfrom = other.do.fields[fname]
34 res.append(sig.eq(eqfrom))
35 return res
36
37 def ports(self):
38 return [self.insn_type,
39 self.insn,
40 self.fn_unit,
41 self.is_32bit,
42 ]