src/soc/fu/spr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.spr.pipeline import SPRBasePipe
  17 from soc.fu.spr.pipe_data import SPRPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to SPRFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_slow_spr1(res, sim, dec2) # FAST1
  29     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # FAST1
  30     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  31     yield from ALUHelpers.get_sim_xer_ov(res, sim, dec2) # XER.ov
  32     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  33
  34     print ("spr get_cu_inputs", res)
  35
  36     return res
  37
  38
  39
  40 def set_alu_inputs(alu, dec2, sim):
  41     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  42     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  43     # and place it into data_i.b
  44
  45     inp = yield from get_cu_inputs(dec2, sim)
  46     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  47     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_ov(alu, dec2, inp)
  49     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  50
  51     yield from ALUHelpers.set_fast_spr1(alu, dec2, inp)
  52     yield from ALUHelpers.set_slow_spr1(alu, dec2, inp)
  53
  54
  55 # This test bench is a bit different than is usual. Initially when I
  56 # was writing it, I had all of the tests call a function to create a
  57 # device under test and simulator, initialize the dut, run the
  58 # simulation for ~2 cycles, and assert that the dut output what it
  59 # should have. However, this was really slow, since it needed to
  60 # create and tear down the dut and simulator for every test case.
  61
  62 # Now, instead of doing that, every test case in SPRTestCase puts some
  63 # data into the test_data list below, describing the instructions to
  64 # be tested and the initial state. Once all the tests have been run,
  65 # test_data gets passed to TestRunner which then sets up the DUT and
  66 # simulator once, runs all the data through it, and asserts that the
  67 # results match the pseudocode sim at every cycle.
  68
  69 # By doing this, I've reduced the time it takes to run the test suite
  70 # massively. Before, it took around 1 minute on my computer, now it
  71 # takes around 3 seconds
  72
  73
  74 class SPRTestCase(FHDLTestCase):
  75     test_data = []
  76
  77     def __init__(self, name):
  78         super().__init__(name)
  79         self.test_name = name
  80
  81     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  82         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  83         self.test_data.append(tc)
  84
  85     def test_1_mfspr(self):
  86         lst = ["mfspr 1, 26", # SRR0
  87                "mfspr 2, 27",  # SRR1
  88                "mfspr 3, 8",  # LR
  89                "mfspr 4, 1",] # XER
  90         initial_regs = [0] * 32
  91         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
  92                         'XER': 0xe00c0000}
  93         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
  94
  95     def test_1_mtspr(self):
  96         lst = ["mtspr 26, 1", # SRR0
  97                "mtspr 27, 2", # SRR1
  98                "mtspr 1, 3",  # XER
  99                "mtspr 9, 4",] # CTR
 100         initial_regs = [0] * 32
 101         initial_regs[1] = 0x129518230011feed
 102         initial_regs[2] = 0x123518230011feed
 103         initial_regs[3] = 0xe00c0000
 104         initial_regs[4] = 0x1010101010101010
 105         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
 106                         'XER': 0x0}
 107         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 108
 109     def test_2_mtspr_mfspr(self):
 110         lst = ["mtspr 26, 1", # SRR0
 111                "mtspr 27, 2", # SRR1
 112                "mtspr 1, 3",  # XER
 113                "mtspr 9, 4",  # CTR
 114                "mfspr 2, 26", # SRR0
 115                "mfspr 3, 27", # and into reg 2
 116                "mfspr 4, 1",  # XER
 117                "mfspr 5, 9",] # CTR
 118         initial_regs = [0] * 32
 119         initial_regs[1] = 0x129518230011feed
 120         initial_regs[2] = 0x123518230011feed
 121         initial_regs[3] = 0xe00c0000
 122         initial_regs[4] = 0x1010101010101010
 123         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
 124                         'XER': 0x0}
 125         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 126
 127     def test_ilang(self):
 128         pspec = SPRPipeSpec(id_wid=2)
 129         alu = SPRBasePipe(pspec)
 130         vl = rtlil.convert(alu, ports=alu.ports())
 131         with open("trap_pipeline.il", "w") as f:
 132             f.write(vl)
 133
 134
 135 class TestRunner(FHDLTestCase):
 136     def __init__(self, test_data):
 137         super().__init__("run_all")
 138         self.test_data = test_data
 139
 140     def run_all(self):
 141         m = Module()
 142         comb = m.d.comb
 143         instruction = Signal(32)
 144
 145         pdecode = create_pdecode()
 146
 147         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 148
 149         pspec = SPRPipeSpec(id_wid=2)
 150         m.submodules.alu = alu = SPRBasePipe(pspec)
 151
 152         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 153         comb += alu.p.valid_i.eq(1)
 154         comb += alu.n.ready_i.eq(1)
 155         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 156         sim = Simulator(m)
 157
 158         sim.add_clock(1e-6)
 159         def process():
 160             for test in self.test_data:
 161                 print("test", test.name)
 162                 print ("sprs", test.sprs)
 163                 program = test.program
 164                 self.subTest(test.name)
 165                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 166                                 test.mem, test.msr)
 167                 gen = program.generate_instructions()
 168                 instructions = list(zip(gen, program.assembly.splitlines()))
 169
 170                 pc = sim.pc.CIA.value
 171                 index = pc//4
 172                 while index < len(instructions):
 173                     ins, code = instructions[index]
 174
 175                     print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
 176                     print(code)
 177
 178                     if 'XER' in sim.spr:
 179                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 180                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 181                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 182                         print ("before: so/ov/32", so, ov, ov32)
 183
 184                     # ask the decoder to decode this binary data (endian'd)
 185                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 186                     yield instruction.eq(ins)          # raw binary instr.
 187                     yield Settle()
 188
 189                     fast_in = yield pdecode2.e.read_fast1.data
 190                     spr_in = yield pdecode2.e.read_spr1.data
 191                     print ("dec2 spr/fast in", fast_in, spr_in)
 192
 193                     fast_out = yield pdecode2.e.write_fast1.data
 194                     spr_out = yield pdecode2.e.write_spr.data
 195                     print ("dec2 spr/fast in", fast_out, spr_out)
 196
 197                     fn_unit = yield pdecode2.e.do.fn_unit
 198                     self.assertEqual(fn_unit, Function.SPR.value)
 199                     yield from set_alu_inputs(alu, pdecode2, sim)
 200                     yield
 201                     opname = code.split(' ')[0]
 202                     yield from sim.call(opname)
 203                     pc = sim.pc.CIA.value
 204                     index = pc//4
 205                     print("pc after %08x" % (pc))
 206
 207                     vld = yield alu.n.valid_o
 208                     while not vld:
 209                         yield
 210                         vld = yield alu.n.valid_o
 211                     yield
 212
 213                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 214
 215         sim.add_sync_process(process)
 216         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
 217                             traces=[]):
 218             sim.run()
 219
 220     def check_alu_outputs(self, alu, dec2, sim, code):
 221
 222         rc = yield dec2.e.do.rc.data
 223         cridx_ok = yield dec2.e.write_cr.ok
 224         cridx = yield dec2.e.write_cr.data
 225
 226         print ("check extra output", repr(code), cridx_ok, cridx)
 227         if rc:
 228             self.assertEqual(cridx, 0, code)
 229
 230         sim_o = {}
 231         res = {}
 232
 233         yield from ALUHelpers.get_int_o(res, alu, dec2)
 234         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
 235         yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
 236         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 237         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 238         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 239
 240         print ("output", res)
 241
 242         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 243         yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
 244         yield from ALUHelpers.get_wr_sim_xer_ov(sim_o, sim, alu, dec2)
 245         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 246         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
 247         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
 248
 249         print ("sim output", sim_o)
 250
 251         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 252         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 253         ALUHelpers.check_xer_so(self, res, sim_o, code)
 254         ALUHelpers.check_int_o(self, res, sim_o, code)
 255         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
 256         ALUHelpers.check_slow_spr1(self, res, sim_o, code)
 257
 258
 259 if __name__ == "__main__":
 260     unittest.main(exit=False)
 261     suite = unittest.TestSuite()
 262     suite.addTest(TestRunner(SPRTestCase.test_data))
 263
 264     runner = unittest.TextTestRunner()
 265     runner.run(suite)