src/soc/fu/spr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.spr.pipeline import SPRBasePipe
  17 from soc.fu.spr.pipe_data import SPRPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to SPRFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_slow_spr1(res, sim, dec2) # FAST1
  29     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # FAST1
  30     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  31     yield from ALUHelpers.get_sim_xer_ov(res, sim, dec2) # XER.ov
  32     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  33
  34     print ("spr get_cu_inputs", res)
  35
  36     return res
  37
  38
  39
  40 def set_alu_inputs(alu, dec2, sim):
  41     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  42     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  43     # and place it into data_i.b
  44
  45     inp = yield from get_cu_inputs(dec2, sim)
  46     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  47     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_ov(alu, dec2, inp)
  49     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  50
  51     yield from ALUHelpers.set_fast_spr1(alu, dec2, inp)
  52     yield from ALUHelpers.set_slow_spr1(alu, dec2, inp)
  53
  54
  55 # This test bench is a bit different than is usual. Initially when I
  56 # was writing it, I had all of the tests call a function to create a
  57 # device under test and simulator, initialize the dut, run the
  58 # simulation for ~2 cycles, and assert that the dut output what it
  59 # should have. However, this was really slow, since it needed to
  60 # create and tear down the dut and simulator for every test case.
  61
  62 # Now, instead of doing that, every test case in SPRTestCase puts some
  63 # data into the test_data list below, describing the instructions to
  64 # be tested and the initial state. Once all the tests have been run,
  65 # test_data gets passed to TestRunner which then sets up the DUT and
  66 # simulator once, runs all the data through it, and asserts that the
  67 # results match the pseudocode sim at every cycle.
  68
  69 # By doing this, I've reduced the time it takes to run the test suite
  70 # massively. Before, it took around 1 minute on my computer, now it
  71 # takes around 3 seconds
  72
  73
  74 class SPRTestCase(FHDLTestCase):
  75     test_data = []
  76
  77     def __init__(self, name):
  78         super().__init__(name)
  79         self.test_name = name
  80
  81     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  82         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  83         self.test_data.append(tc)
  84
  85     def test_1_mfspr(self):
  86         lst = ["mfspr 1, 26", # SRR0
  87                "mfspr 2, 27",  # SRR1
  88                "mfspr 2, 8",] # LR
  89         initial_regs = [0] * 32
  90         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234}
  91         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
  92
  93     def test_ilang(self):
  94         pspec = SPRPipeSpec(id_wid=2)
  95         alu = SPRBasePipe(pspec)
  96         vl = rtlil.convert(alu, ports=alu.ports())
  97         with open("trap_pipeline.il", "w") as f:
  98             f.write(vl)
  99
 100
 101 class TestRunner(FHDLTestCase):
 102     def __init__(self, test_data):
 103         super().__init__("run_all")
 104         self.test_data = test_data
 105
 106     def run_all(self):
 107         m = Module()
 108         comb = m.d.comb
 109         instruction = Signal(32)
 110
 111         pdecode = create_pdecode()
 112
 113         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 114
 115         pspec = SPRPipeSpec(id_wid=2)
 116         m.submodules.alu = alu = SPRBasePipe(pspec)
 117
 118         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 119         comb += alu.p.valid_i.eq(1)
 120         comb += alu.n.ready_i.eq(1)
 121         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 122         sim = Simulator(m)
 123
 124         sim.add_clock(1e-6)
 125         def process():
 126             for test in self.test_data:
 127                 print("test", test.name)
 128                 print ("sprs", test.sprs)
 129                 program = test.program
 130                 self.subTest(test.name)
 131                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 132                                 test.mem, test.msr)
 133                 gen = program.generate_instructions()
 134                 instructions = list(zip(gen, program.assembly.splitlines()))
 135
 136                 pc = sim.pc.CIA.value
 137                 index = pc//4
 138                 while index < len(instructions):
 139                     ins, code = instructions[index]
 140
 141                     print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
 142                     print(code)
 143
 144                     if 'XER' in sim.spr:
 145                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 146                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 147                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 148                         print ("before: so/ov/32", so, ov, ov32)
 149
 150                     # ask the decoder to decode this binary data (endian'd)
 151                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 152                     yield instruction.eq(ins)          # raw binary instr.
 153                     yield Settle()
 154
 155                     fast_in = yield pdecode2.e.read_fast1.data
 156                     spr_in = yield pdecode2.e.read_spr1.data
 157                     print ("dec2 spr/fast in", fast_in, spr_in)
 158
 159                     fast_out = yield pdecode2.e.write_fast1.data
 160                     spr_out = yield pdecode2.e.write_spr.data
 161                     print ("dec2 spr/fast in", fast_out, spr_out)
 162
 163                     fn_unit = yield pdecode2.e.do.fn_unit
 164                     self.assertEqual(fn_unit, Function.SPR.value)
 165                     yield from set_alu_inputs(alu, pdecode2, sim)
 166                     yield
 167                     opname = code.split(' ')[0]
 168                     yield from sim.call(opname)
 169                     pc = sim.pc.CIA.value
 170                     index = pc//4
 171                     print("pc after %08x" % (pc))
 172
 173                     vld = yield alu.n.valid_o
 174                     while not vld:
 175                         yield
 176                         vld = yield alu.n.valid_o
 177                     yield
 178
 179                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 180
 181         sim.add_sync_process(process)
 182         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
 183                             traces=[]):
 184             sim.run()
 185
 186     def check_alu_outputs(self, alu, dec2, sim, code):
 187
 188         rc = yield dec2.e.do.rc.data
 189         cridx_ok = yield dec2.e.write_cr.ok
 190         cridx = yield dec2.e.write_cr.data
 191
 192         print ("check extra output", repr(code), cridx_ok, cridx)
 193         if rc:
 194             self.assertEqual(cridx, 0, code)
 195
 196         sim_o = {}
 197         res = {}
 198
 199         yield from ALUHelpers.get_int_o(res, alu, dec2)
 200         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
 201         yield from ALUHelpers.get_slow_spr1(res, alu, dec2)
 202         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 203         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 204         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 205
 206         print ("output", res)
 207
 208         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 209         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 210         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 211         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 212         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
 213         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
 214
 215         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 216         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 217         ALUHelpers.check_int_o(self, res, sim_o, code)
 218         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
 219         ALUHelpers.check_slow_spr1(self, res, sim_o, code)
 220         ALUHelpers.check_xer_so(self, res, sim_o, code)
 221
 222
 223 if __name__ == "__main__":
 224     unittest.main(exit=False)
 225     suite = unittest.TestSuite()
 226     suite.addTest(TestRunner(SPRTestCase.test_data))
 227
 228     runner = unittest.TextTestRunner()
 229     runner.run(suite)