3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
9 from soc
.decoder
.power_enums
import XER_bits
, CryIn
, spr_dict
10 from soc
.regfile
.util
import fast_reg_to_spr
, slow_reg_to_spr
# HACK!
11 from soc
.regfile
.regfiles
import XERRegs
, FastRegs
14 # TODO: make this a util routine (somewhere)
15 def mask_extend(x
, nbits
, repeat
):
17 extended
= (1<<repeat
)-1
18 for i
in range(nbits
):
20 res |
= extended
<< (i
*repeat
)
24 class SkipCase(Exception):
25 """Raise this exception to skip a test case.
27 Usually you'd use one of the skip_case* decorators.
29 For use with TestAccumulatorBase
34 """identity function"""
38 def skip_case(reason
):
40 Unconditionally skip a test case.
43 @skip_case("my reason for skipping")
51 For use with TestAccumulatorBase
54 assert not isinstance(item
, type), \
55 "can't use skip_case to decorate types"
57 @functools.wraps(item
)
58 def wrapper(*args
, **kwargs
):
59 raise SkipCase(reason
)
61 if isinstance(reason
, types
.FunctionType
):
64 return decorator(item
)
68 def skip_case_if(condition
, reason
):
70 Conditionally skip a test case.
73 @skip_case_if(should_i_skip(), "my reason for skipping")
77 For use with TestAccumulatorBase
80 return skip_case(reason
)
84 class TestAccumulatorBase
:
88 # automatically identifies anything starting with "case_" and
89 # runs it. very similar to unittest auto-identification except
90 # we need a different system
91 for n
, v
in self
.__class
__.__dict
__.items():
92 if n
.startswith("case_") and callable(v
):
96 # TODO(programmerjake): translate to final test sending
97 # skip signal to unittest. for now, just print the skipped
99 print(f
"SKIPPED({n}):", str(e
))
101 def add_case(self
, prog
, initial_regs
=None, initial_sprs
=None,
102 initial_cr
=0, initial_msr
=0,
105 test_name
= inspect
.stack()[1][3] # name of caller of this function
106 tc
= TestCase(prog
, test_name
,
107 regs
=initial_regs
, sprs
=initial_sprs
, cr
=initial_cr
,
111 self
.test_data
.append(tc
)
115 def __init__(self
, program
, name
, regs
=None, sprs
=None, cr
=0, mem
=None,
118 extra_break_addr
=None):
120 self
.program
= program
135 self
.extra_break_addr
= extra_break_addr
140 def get_sim_fast_reg(res
, sim
, dec2
, reg
, name
):
141 spr_sel
= fast_reg_to_spr(reg
)
142 spr_data
= sim
.spr
[spr_sel
].value
145 def get_sim_cia(res
, sim
, dec2
):
146 res
['cia'] = sim
.pc
.CIA
.value
148 # use this *after* the simulation has run a step (it returns CIA)
149 def get_sim_nia(res
, sim
, dec2
):
150 res
['nia'] = sim
.pc
.CIA
.value
152 def get_sim_msr(res
, sim
, dec2
):
153 res
['msr'] = sim
.msr
.value
155 def get_sim_slow_spr1(res
, sim
, dec2
):
156 spr1_en
= yield dec2
.e
.read_spr1
.ok
158 spr1_sel
= yield dec2
.e
.read_spr1
.data
159 spr1_sel
= slow_reg_to_spr(spr1_sel
)
160 spr1_data
= sim
.spr
[spr1_sel
].value
161 res
['spr1'] = spr1_data
163 def get_sim_fast_spr1(res
, sim
, dec2
):
164 fast1_en
= yield dec2
.e
.read_fast1
.ok
166 fast1_sel
= yield dec2
.e
.read_fast1
.data
167 spr1_sel
= fast_reg_to_spr(fast1_sel
)
168 spr1_data
= sim
.spr
[spr1_sel
].value
169 res
['fast1'] = spr1_data
171 def get_sim_fast_spr2(res
, sim
, dec2
):
172 fast2_en
= yield dec2
.e
.read_fast2
.ok
174 fast2_sel
= yield dec2
.e
.read_fast2
.data
175 spr2_sel
= fast_reg_to_spr(fast2_sel
)
176 spr2_data
= sim
.spr
[spr2_sel
].value
177 res
['fast2'] = spr2_data
179 def get_sim_cr_a(res
, sim
, dec2
):
180 cridx_ok
= yield dec2
.e
.read_cr1
.ok
182 cridx
= yield dec2
.e
.read_cr1
.data
183 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
185 def get_sim_cr_b(res
, sim
, dec2
):
186 cridx_ok
= yield dec2
.e
.read_cr2
.ok
188 cridx
= yield dec2
.e
.read_cr2
.data
189 res
['cr_b'] = sim
.crl
[cridx
].get_range().value
191 def get_sim_cr_c(res
, sim
, dec2
):
192 cridx_ok
= yield dec2
.e
.read_cr3
.ok
194 cridx
= yield dec2
.e
.read_cr3
.data
195 res
['cr_c'] = sim
.crl
[cridx
].get_range().value
197 def get_sim_int_ra(res
, sim
, dec2
):
198 # TODO: immediate RA zero
199 reg1_ok
= yield dec2
.e
.read_reg1
.ok
201 data1
= yield dec2
.e
.read_reg1
.data
202 res
['ra'] = sim
.gpr(data1
).value
204 def get_sim_int_rb(res
, sim
, dec2
):
205 reg2_ok
= yield dec2
.e
.read_reg2
.ok
207 data
= yield dec2
.e
.read_reg2
.data
208 res
['rb'] = sim
.gpr(data
).value
210 def get_sim_int_rc(res
, sim
, dec2
):
211 reg3_ok
= yield dec2
.e
.read_reg3
.ok
213 data
= yield dec2
.e
.read_reg3
.data
214 res
['rc'] = sim
.gpr(data
).value
216 def get_rd_sim_xer_ca(res
, sim
, dec2
):
217 cry_in
= yield dec2
.e
.do
.input_carry
218 xer_in
= yield dec2
.e
.xer_in
219 if (xer_in
& (1<<XERRegs
.CA
)) or cry_in
== CryIn
.CA
.value
:
220 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
221 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
222 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
224 def set_int_ra(alu
, dec2
, inp
):
225 # TODO: immediate RA zero.
227 yield alu
.p
.data_i
.ra
.eq(inp
['ra'])
229 yield alu
.p
.data_i
.ra
.eq(0)
231 def set_int_rb(alu
, dec2
, inp
):
232 yield alu
.p
.data_i
.rb
.eq(0)
234 yield alu
.p
.data_i
.rb
.eq(inp
['rb'])
235 if not hasattr(dec2
.e
.do
, "imm_data"):
237 # If there's an immediate, set the B operand to that
238 imm_ok
= yield dec2
.e
.do
.imm_data
.ok
240 data2
= yield dec2
.e
.do
.imm_data
.data
241 yield alu
.p
.data_i
.rb
.eq(data2
)
243 def set_int_rc(alu
, dec2
, inp
):
245 yield alu
.p
.data_i
.rc
.eq(inp
['rc'])
247 yield alu
.p
.data_i
.rc
.eq(0)
249 def set_xer_ca(alu
, dec2
, inp
):
251 yield alu
.p
.data_i
.xer_ca
.eq(inp
['xer_ca'])
252 print("extra inputs: CA/32", bin(inp
['xer_ca']))
254 def set_xer_ov(alu
, dec2
, inp
):
256 yield alu
.p
.data_i
.xer_ov
.eq(inp
['xer_ov'])
257 print("extra inputs: OV/32", bin(inp
['xer_ov']))
259 def set_xer_so(alu
, dec2
, inp
):
262 print("extra inputs: so", so
)
263 yield alu
.p
.data_i
.xer_so
.eq(so
)
265 def set_msr(alu
, dec2
, inp
):
266 print("TODO: deprecate set_msr")
268 yield alu
.p
.data_i
.msr
.eq(inp
['msr'])
270 def set_cia(alu
, dec2
, inp
):
271 print("TODO: deprecate set_cia")
273 yield alu
.p
.data_i
.cia
.eq(inp
['cia'])
275 def set_slow_spr1(alu
, dec2
, inp
):
277 yield alu
.p
.data_i
.spr1
.eq(inp
['spr1'])
279 def set_slow_spr2(alu
, dec2
, inp
):
281 yield alu
.p
.data_i
.spr2
.eq(inp
['spr2'])
283 def set_fast_spr1(alu
, dec2
, inp
):
285 yield alu
.p
.data_i
.fast1
.eq(inp
['fast1'])
287 def set_fast_spr2(alu
, dec2
, inp
):
289 yield alu
.p
.data_i
.fast2
.eq(inp
['fast2'])
291 def set_cr_a(alu
, dec2
, inp
):
293 yield alu
.p
.data_i
.cr_a
.eq(inp
['cr_a'])
295 def set_cr_b(alu
, dec2
, inp
):
297 yield alu
.p
.data_i
.cr_b
.eq(inp
['cr_b'])
299 def set_cr_c(alu
, dec2
, inp
):
301 yield alu
.p
.data_i
.cr_c
.eq(inp
['cr_c'])
303 def set_full_cr(alu
, dec2
, inp
):
305 full_reg
= yield dec2
.dec_cr_in
.whole_reg
.data
306 full_reg_ok
= yield dec2
.dec_cr_in
.whole_reg
.ok
307 full_cr_mask
= mask_extend(full_reg
, 8, 4)
308 yield alu
.p
.data_i
.full_cr
.eq(inp
['full_cr'] & full_cr_mask
)
310 yield alu
.p
.data_i
.full_cr
.eq(0)
312 def get_slow_spr1(res
, alu
, dec2
):
313 spr1_valid
= yield alu
.n
.data_o
.spr1
.ok
315 res
['spr1'] = yield alu
.n
.data_o
.spr1
.data
317 def get_slow_spr2(res
, alu
, dec2
):
318 spr2_valid
= yield alu
.n
.data_o
.spr2
.ok
320 res
['spr2'] = yield alu
.n
.data_o
.spr2
.data
322 def get_fast_spr1(res
, alu
, dec2
):
323 spr1_valid
= yield alu
.n
.data_o
.fast1
.ok
325 res
['fast1'] = yield alu
.n
.data_o
.fast1
.data
327 def get_fast_spr2(res
, alu
, dec2
):
328 spr2_valid
= yield alu
.n
.data_o
.fast2
.ok
330 res
['fast2'] = yield alu
.n
.data_o
.fast2
.data
332 def get_cia(res
, alu
, dec2
):
333 res
['cia'] = yield alu
.p
.data_i
.cia
335 def get_nia(res
, alu
, dec2
):
336 nia_valid
= yield alu
.n
.data_o
.nia
.ok
338 res
['nia'] = yield alu
.n
.data_o
.nia
.data
340 def get_msr(res
, alu
, dec2
):
341 msr_valid
= yield alu
.n
.data_o
.msr
.ok
343 res
['msr'] = yield alu
.n
.data_o
.msr
.data
345 def get_int_o1(res
, alu
, dec2
):
346 out_reg_valid
= yield dec2
.e
.write_ea
.ok
348 res
['o1'] = yield alu
.n
.data_o
.o1
.data
350 def get_int_o(res
, alu
, dec2
):
351 out_reg_valid
= yield dec2
.e
.write_reg
.ok
353 res
['o'] = yield alu
.n
.data_o
.o
.data
355 def get_cr_a(res
, alu
, dec2
):
356 cridx_ok
= yield dec2
.e
.write_cr
.ok
358 res
['cr_a'] = yield alu
.n
.data_o
.cr0
.data
360 def get_xer_so(res
, alu
, dec2
):
361 oe
= yield dec2
.e
.do
.oe
.oe
362 oe_ok
= yield dec2
.e
.do
.oe
.ok
363 xer_out
= yield dec2
.e
.xer_out
364 if not (yield alu
.n
.data_o
.xer_so
.ok
):
366 if xer_out
or (oe
and oe_ok
):
367 res
['xer_so'] = yield alu
.n
.data_o
.xer_so
.data
[0]
369 def get_xer_ov(res
, alu
, dec2
):
370 oe
= yield dec2
.e
.do
.oe
.oe
371 oe_ok
= yield dec2
.e
.do
.oe
.ok
372 xer_out
= yield dec2
.e
.xer_out
373 if not (yield alu
.n
.data_o
.xer_ov
.ok
):
375 if xer_out
or (oe
and oe_ok
):
376 res
['xer_ov'] = yield alu
.n
.data_o
.xer_ov
.data
378 def get_xer_ca(res
, alu
, dec2
):
379 cry_out
= yield dec2
.e
.do
.output_carry
380 xer_out
= yield dec2
.e
.xer_out
381 if not (yield alu
.n
.data_o
.xer_ca
.ok
):
383 if xer_out
or (cry_out
):
384 res
['xer_ca'] = yield alu
.n
.data_o
.xer_ca
.data
386 def get_sim_int_o(res
, sim
, dec2
):
387 out_reg_valid
= yield dec2
.e
.write_reg
.ok
389 write_reg_idx
= yield dec2
.e
.write_reg
.data
390 res
['o'] = sim
.gpr(write_reg_idx
).value
392 def get_sim_int_o1(res
, sim
, dec2
):
393 out_reg_valid
= yield dec2
.e
.write_ea
.ok
395 write_reg_idx
= yield dec2
.e
.write_ea
.data
396 res
['o1'] = sim
.gpr(write_reg_idx
).value
398 def get_wr_sim_cr_a(res
, sim
, dec2
):
399 cridx_ok
= yield dec2
.e
.write_cr
.ok
401 cridx
= yield dec2
.e
.write_cr
.data
402 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
404 def get_wr_fast_spr2(res
, sim
, dec2
):
405 ok
= yield dec2
.e
.write_fast2
.ok
407 spr_num
= yield dec2
.e
.write_fast2
.data
408 spr_num
= fast_reg_to_spr(spr_num
)
409 spr_name
= spr_dict
[spr_num
].SPR
410 res
['fast2'] = sim
.spr
[spr_name
].value
412 def get_wr_fast_spr1(res
, sim
, dec2
):
413 ok
= yield dec2
.e
.write_fast1
.ok
415 spr_num
= yield dec2
.e
.write_fast1
.data
416 spr_num
= fast_reg_to_spr(spr_num
)
417 spr_name
= spr_dict
[spr_num
].SPR
418 res
['fast1'] = sim
.spr
[spr_name
].value
420 def get_wr_slow_spr1(res
, sim
, dec2
):
421 ok
= yield dec2
.e
.write_spr
.ok
423 spr_num
= yield dec2
.e
.write_spr
.data
424 spr_num
= slow_reg_to_spr(spr_num
)
425 spr_name
= spr_dict
[spr_num
].SPR
426 res
['spr1'] = sim
.spr
[spr_name
].value
428 def get_wr_sim_xer_ca(res
, sim
, dec2
):
429 # if not (yield alu.n.data_o.xer_ca.ok):
431 cry_out
= yield dec2
.e
.do
.output_carry
432 xer_out
= yield dec2
.e
.xer_out
433 if cry_out
or xer_out
:
434 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
435 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
436 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
438 def get_wr_sim_xer_ov(res
, sim
, alu
, dec2
):
439 oe
= yield dec2
.e
.do
.oe
.oe
440 oe_ok
= yield dec2
.e
.do
.oe
.ok
441 xer_out
= yield dec2
.e
.xer_out
442 print("get_wr_sim_xer_ov", xer_out
)
443 if not (yield alu
.n
.data_o
.xer_ov
.ok
):
445 if xer_out
or (oe
and oe_ok
):
446 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
447 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
448 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
450 def get_wr_sim_xer_so(res
, sim
, alu
, dec2
):
451 oe
= yield dec2
.e
.do
.oe
.oe
452 oe_ok
= yield dec2
.e
.do
.oe
.ok
453 xer_out
= yield dec2
.e
.xer_out
454 if not (yield alu
.n
.data_o
.xer_so
.ok
):
456 if xer_out
or (oe
and oe_ok
):
457 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
459 def get_sim_xer_ov(res
, sim
, dec2
):
460 oe
= yield dec2
.e
.do
.oe
.oe
461 oe_ok
= yield dec2
.e
.do
.oe
.ok
462 xer_in
= yield dec2
.e
.xer_in
463 print("get_sim_xer_ov", xer_in
)
464 if (xer_in
& (1<<XERRegs
.OV
)) or (oe
and oe_ok
):
465 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
466 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
467 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
469 def get_sim_xer_so(res
, sim
, dec2
):
470 print ("XER", sim
.spr
.__class
__, sim
.spr
, sim
.spr
['XER'])
471 oe
= yield dec2
.e
.do
.oe
.oe
472 oe_ok
= yield dec2
.e
.do
.oe
.ok
473 xer_in
= yield dec2
.e
.xer_in
474 rc
= yield dec2
.e
.do
.rc
.rc
475 rc_ok
= yield dec2
.e
.do
.rc
.ok
476 if (xer_in
& (1<<XERRegs
.SO
)) or (oe
and oe_ok
) or (rc
and rc_ok
):
477 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
479 def check_slow_spr1(dut
, res
, sim_o
, msg
):
481 expected
= sim_o
['spr1']
482 alu_out
= res
['spr1']
483 print(f
"expected {expected:x}, actual: {alu_out:x}")
484 dut
.assertEqual(expected
, alu_out
, msg
)
486 def check_fast_spr1(dut
, res
, sim_o
, msg
):
488 expected
= sim_o
['fast1']
489 alu_out
= res
['fast1']
490 print(f
"expected {expected:x}, actual: {alu_out:x}")
491 dut
.assertEqual(expected
, alu_out
, msg
)
493 def check_fast_spr2(dut
, res
, sim_o
, msg
):
495 expected
= sim_o
['fast2']
496 alu_out
= res
['fast2']
497 print(f
"expected {expected:x}, actual: {alu_out:x}")
498 dut
.assertEqual(expected
, alu_out
, msg
)
500 def check_int_o1(dut
, res
, sim_o
, msg
):
502 expected
= sim_o
['o1']
504 print(f
"expected {expected:x}, actual: {alu_out:x}")
505 dut
.assertEqual(expected
, alu_out
, msg
)
507 def check_int_o(dut
, res
, sim_o
, msg
):
509 expected
= sim_o
['o']
511 print(f
"expected int sim {expected:x}, actual: {alu_out:x}")
512 dut
.assertEqual(expected
, alu_out
, msg
)
514 def check_msr(dut
, res
, sim_o
, msg
):
516 expected
= sim_o
['msr']
518 print(f
"expected {expected:x}, actual: {alu_out:x}")
519 dut
.assertEqual(expected
, alu_out
, msg
)
521 def check_nia(dut
, res
, sim_o
, msg
):
523 expected
= sim_o
['nia']
525 print(f
"expected {expected:x}, actual: {alu_out:x}")
526 dut
.assertEqual(expected
, alu_out
, msg
)
528 def check_cr_a(dut
, res
, sim_o
, msg
):
530 cr_expected
= sim_o
['cr_a']
531 cr_actual
= res
['cr_a']
532 print("CR", cr_expected
, cr_actual
)
533 dut
.assertEqual(cr_expected
, cr_actual
, msg
)
535 def check_xer_ca(dut
, res
, sim_o
, msg
):
537 ca_expected
= sim_o
['xer_ca']
538 ca_actual
= res
['xer_ca']
539 print("CA", ca_expected
, ca_actual
)
540 dut
.assertEqual(ca_expected
, ca_actual
, msg
)
542 def check_xer_ov(dut
, res
, sim_o
, msg
):
544 ov_expected
= sim_o
['xer_ov']
545 ov_actual
= res
['xer_ov']
546 print("OV", ov_expected
, ov_actual
)
547 dut
.assertEqual(ov_expected
, ov_actual
, msg
)
549 def check_xer_so(dut
, res
, sim_o
, msg
):
551 so_expected
= sim_o
['xer_so']
552 so_actual
= res
['xer_so']
553 print("SO", so_expected
, so_actual
)
554 dut
.assertEqual(so_expected
, so_actual
, msg
)