src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 import inspect
   7 import functools
   8 import types
   9 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
  10 from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr  # HACK!
  11 from soc.regfile.regfiles import XERRegs, FastRegs
  12
  13
  14 # TODO: make this a util routine (somewhere)
  15 def mask_extend(x, nbits, repeat):
  16     res = 0
  17     extended = (1<<repeat)-1
  18     for i in range(nbits):
  19         if x & (1<<i):
  20             res |= extended << (i*repeat)
  21     return res
  22
  23
  24 class SkipCase(Exception):
  25     """Raise this exception to skip a test case.
  26
  27     Usually you'd use one of the skip_case* decorators.
  28
  29     For use with TestAccumulatorBase
  30     """
  31
  32
  33 def _id(obj):
  34     """identity function"""
  35     return obj
  36
  37
  38 def skip_case(reason):
  39     """
  40     Unconditionally skip a test case.
  41
  42     Use like:
  43         @skip_case("my reason for skipping")
  44         def case_abc(self):
  45             ...
  46     or:
  47         @skip_case
  48         def case_def(self):
  49             ...
  50
  51     For use with TestAccumulatorBase
  52     """
  53     def decorator(item):
  54         assert not isinstance(item, type), \
  55             "can't use skip_case to decorate types"
  56
  57         @functools.wraps(item)
  58         def wrapper(*args, **kwargs):
  59             raise SkipCase(reason)
  60         return wrapper
  61     if isinstance(reason, types.FunctionType):
  62         item = reason
  63         reason = ""
  64         return decorator(item)
  65     return decorator
  66
  67
  68 def skip_case_if(condition, reason):
  69     """
  70     Conditionally skip a test case.
  71
  72     Use like:
  73         @skip_case_if(should_i_skip(), "my reason for skipping")
  74         def case_abc(self):
  75             ...
  76
  77     For use with TestAccumulatorBase
  78     """
  79     if condition:
  80         return skip_case(reason)
  81     return _id
  82
  83
  84 class TestAccumulatorBase:
  85
  86     def __init__(self):
  87         self.test_data = []
  88         # automatically identifies anything starting with "case_" and
  89         # runs it.  very similar to unittest auto-identification except
  90         # we need a different system
  91         for n, v in self.__class__.__dict__.items():
  92             if n.startswith("case_") and callable(v):
  93                 try:
  94                     v(self)
  95                 except SkipCase as e:
  96                     # TODO(programmerjake): translate to final test sending
  97                     # skip signal to unittest. for now, just print the skipped
  98                     # reason and ignore
  99                     print(f"SKIPPED({n}):", str(e))
 100
 101     def add_case(self, prog, initial_regs=None, initial_sprs=None,
 102                  initial_cr=0, initial_msr=0,
 103                  initial_mem=None):
 104
 105         test_name = inspect.stack()[1][3]  # name of caller of this function
 106         tc = TestCase(prog, test_name,
 107                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
 108                       msr=initial_msr,
 109                       mem=initial_mem)
 110
 111         self.test_data.append(tc)
 112
 113
 114 class TestCase:
 115     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
 116                  msr=0,
 117                  do_sim=True,
 118                  extra_break_addr=None):
 119
 120         self.program = program
 121         self.name = name
 122
 123         if regs is None:
 124             regs = [0] * 32
 125         if sprs is None:
 126             sprs = {}
 127         if mem is None:
 128             mem = {}
 129         self.regs = regs
 130         self.sprs = sprs
 131         self.cr = cr
 132         self.mem = mem
 133         self.msr = msr
 134         self.do_sim = do_sim
 135         self.extra_break_addr = extra_break_addr
 136
 137
 138 class ALUHelpers:
 139
 140     def get_sim_fast_reg(res, sim, dec2, reg, name):
 141         spr_sel = fast_reg_to_spr(reg)
 142         spr_data = sim.spr[spr_sel].value
 143         res[name] = spr_data
 144
 145     def get_sim_cia(res, sim, dec2):
 146         res['cia'] = sim.pc.CIA.value
 147
 148     # use this *after* the simulation has run a step (it returns CIA)
 149     def get_sim_nia(res, sim, dec2):
 150         res['nia'] = sim.pc.CIA.value
 151
 152     def get_sim_msr(res, sim, dec2):
 153         res['msr'] = sim.msr.value
 154
 155     def get_sim_slow_spr1(res, sim, dec2):
 156         spr1_en = yield dec2.e.read_spr1.ok
 157         if spr1_en:
 158             spr1_sel = yield dec2.e.read_spr1.data
 159             spr1_sel = slow_reg_to_spr(spr1_sel)
 160             spr1_data = sim.spr[spr1_sel].value
 161             res['spr1'] = spr1_data
 162
 163     def get_sim_fast_spr1(res, sim, dec2):
 164         fast1_en = yield dec2.e.read_fast1.ok
 165         if fast1_en:
 166             fast1_sel = yield dec2.e.read_fast1.data
 167             spr1_sel = fast_reg_to_spr(fast1_sel)
 168             spr1_data = sim.spr[spr1_sel].value
 169             res['fast1'] = spr1_data
 170
 171     def get_sim_fast_spr2(res, sim, dec2):
 172         fast2_en = yield dec2.e.read_fast2.ok
 173         if fast2_en:
 174             fast2_sel = yield dec2.e.read_fast2.data
 175             spr2_sel = fast_reg_to_spr(fast2_sel)
 176             spr2_data = sim.spr[spr2_sel].value
 177             res['fast2'] = spr2_data
 178
 179     def get_sim_cr_a(res, sim, dec2):
 180         cridx_ok = yield dec2.e.read_cr1.ok
 181         if cridx_ok:
 182             cridx = yield dec2.e.read_cr1.data
 183             res['cr_a'] = sim.crl[cridx].get_range().value
 184
 185     def get_sim_cr_b(res, sim, dec2):
 186         cridx_ok = yield dec2.e.read_cr2.ok
 187         if cridx_ok:
 188             cridx = yield dec2.e.read_cr2.data
 189             res['cr_b'] = sim.crl[cridx].get_range().value
 190
 191     def get_sim_cr_c(res, sim, dec2):
 192         cridx_ok = yield dec2.e.read_cr3.ok
 193         if cridx_ok:
 194             cridx = yield dec2.e.read_cr3.data
 195             res['cr_c'] = sim.crl[cridx].get_range().value
 196
 197     def get_sim_int_ra(res, sim, dec2):
 198         # TODO: immediate RA zero
 199         reg1_ok = yield dec2.e.read_reg1.ok
 200         if reg1_ok:
 201             data1 = yield dec2.e.read_reg1.data
 202             res['ra'] = sim.gpr(data1).value
 203
 204     def get_sim_int_rb(res, sim, dec2):
 205         reg2_ok = yield dec2.e.read_reg2.ok
 206         if reg2_ok:
 207             data = yield dec2.e.read_reg2.data
 208             res['rb'] = sim.gpr(data).value
 209
 210     def get_sim_int_rc(res, sim, dec2):
 211         reg3_ok = yield dec2.e.read_reg3.ok
 212         if reg3_ok:
 213             data = yield dec2.e.read_reg3.data
 214             res['rc'] = sim.gpr(data).value
 215
 216     def get_rd_sim_xer_ca(res, sim, dec2):
 217         cry_in = yield dec2.e.do.input_carry
 218         xer_in = yield dec2.e.xer_in
 219         if (xer_in & (1<<XERRegs.CA)) or cry_in == CryIn.CA.value:
 220             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 221             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 222             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 223
 224     def set_int_ra(alu, dec2, inp):
 225         # TODO: immediate RA zero.
 226         if 'ra' in inp:
 227             yield alu.p.data_i.ra.eq(inp['ra'])
 228         else:
 229             yield alu.p.data_i.ra.eq(0)
 230
 231     def set_int_rb(alu, dec2, inp):
 232         yield alu.p.data_i.rb.eq(0)
 233         if 'rb' in inp:
 234             yield alu.p.data_i.rb.eq(inp['rb'])
 235         # If there's an immediate, set the B operand to that
 236         imm_ok = yield dec2.e.do.imm_data.ok
 237         if imm_ok:
 238             data2 = yield dec2.e.do.imm_data.data
 239             yield alu.p.data_i.rb.eq(data2)
 240
 241     def set_int_rc(alu, dec2, inp):
 242         if 'rc' in inp:
 243             yield alu.p.data_i.rc.eq(inp['rc'])
 244         else:
 245             yield alu.p.data_i.rc.eq(0)
 246
 247     def set_xer_ca(alu, dec2, inp):
 248         if 'xer_ca' in inp:
 249             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 250             print("extra inputs: CA/32", bin(inp['xer_ca']))
 251
 252     def set_xer_ov(alu, dec2, inp):
 253         if 'xer_ov' in inp:
 254             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 255             print("extra inputs: OV/32", bin(inp['xer_ov']))
 256
 257     def set_xer_so(alu, dec2, inp):
 258         if 'xer_so' in inp:
 259             so = inp['xer_so']
 260             print("extra inputs: so", so)
 261             yield alu.p.data_i.xer_so.eq(so)
 262
 263     def set_msr(alu, dec2, inp):
 264         print("TODO: deprecate set_msr")
 265         if 'msr' in inp:
 266             yield alu.p.data_i.msr.eq(inp['msr'])
 267
 268     def set_cia(alu, dec2, inp):
 269         print("TODO: deprecate set_cia")
 270         if 'cia' in inp:
 271             yield alu.p.data_i.cia.eq(inp['cia'])
 272
 273     def set_slow_spr1(alu, dec2, inp):
 274         if 'spr1' in inp:
 275             yield alu.p.data_i.spr1.eq(inp['spr1'])
 276
 277     def set_slow_spr2(alu, dec2, inp):
 278         if 'spr2' in inp:
 279             yield alu.p.data_i.spr2.eq(inp['spr2'])
 280
 281     def set_fast_spr1(alu, dec2, inp):
 282         if 'fast1' in inp:
 283             yield alu.p.data_i.fast1.eq(inp['fast1'])
 284
 285     def set_fast_spr2(alu, dec2, inp):
 286         if 'fast2' in inp:
 287             yield alu.p.data_i.fast2.eq(inp['fast2'])
 288
 289     def set_cr_a(alu, dec2, inp):
 290         if 'cr_a' in inp:
 291             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 292
 293     def set_cr_b(alu, dec2, inp):
 294         if 'cr_b' in inp:
 295             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 296
 297     def set_cr_c(alu, dec2, inp):
 298         if 'cr_c' in inp:
 299             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 300
 301     def set_full_cr(alu, dec2, inp):
 302         if 'full_cr' in inp:
 303             full_reg = yield dec2.e.do.read_cr_whole.data
 304             full_reg_ok = yield dec2.e.do.read_cr_whole.ok
 305             full_cr_mask = mask_extend(full_reg, 8, 4)
 306             yield alu.p.data_i.full_cr.eq(inp['full_cr'] & full_cr_mask)
 307         else:
 308             yield alu.p.data_i.full_cr.eq(0)
 309
 310     def get_slow_spr1(res, alu, dec2):
 311         spr1_valid = yield alu.n.data_o.spr1.ok
 312         if spr1_valid:
 313             res['spr1'] = yield alu.n.data_o.spr1.data
 314
 315     def get_slow_spr2(res, alu, dec2):
 316         spr2_valid = yield alu.n.data_o.spr2.ok
 317         if spr2_valid:
 318             res['spr2'] = yield alu.n.data_o.spr2.data
 319
 320     def get_fast_spr1(res, alu, dec2):
 321         spr1_valid = yield alu.n.data_o.fast1.ok
 322         if spr1_valid:
 323             res['fast1'] = yield alu.n.data_o.fast1.data
 324
 325     def get_fast_spr2(res, alu, dec2):
 326         spr2_valid = yield alu.n.data_o.fast2.ok
 327         if spr2_valid:
 328             res['fast2'] = yield alu.n.data_o.fast2.data
 329
 330     def get_cia(res, alu, dec2):
 331         res['cia'] = yield alu.p.data_i.cia
 332
 333     def get_nia(res, alu, dec2):
 334         nia_valid = yield alu.n.data_o.nia.ok
 335         if nia_valid:
 336             res['nia'] = yield alu.n.data_o.nia.data
 337
 338     def get_msr(res, alu, dec2):
 339         msr_valid = yield alu.n.data_o.msr.ok
 340         if msr_valid:
 341             res['msr'] = yield alu.n.data_o.msr.data
 342
 343     def get_int_o1(res, alu, dec2):
 344         out_reg_valid = yield dec2.e.write_ea.ok
 345         if out_reg_valid:
 346             res['o1'] = yield alu.n.data_o.o1.data
 347
 348     def get_int_o(res, alu, dec2):
 349         out_reg_valid = yield dec2.e.write_reg.ok
 350         if out_reg_valid:
 351             res['o'] = yield alu.n.data_o.o.data
 352
 353     def get_cr_a(res, alu, dec2):
 354         cridx_ok = yield dec2.e.write_cr.ok
 355         if cridx_ok:
 356             res['cr_a'] = yield alu.n.data_o.cr0.data
 357
 358     def get_xer_so(res, alu, dec2):
 359         oe = yield dec2.e.do.oe.oe
 360         oe_ok = yield dec2.e.do.oe.ok
 361         xer_out = yield dec2.e.xer_out
 362         if not (yield alu.n.data_o.xer_so.ok):
 363             return
 364         if xer_out or (oe and oe_ok):
 365             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 366
 367     def get_xer_ov(res, alu, dec2):
 368         oe = yield dec2.e.do.oe.oe
 369         oe_ok = yield dec2.e.do.oe.ok
 370         xer_out = yield dec2.e.xer_out
 371         if not (yield alu.n.data_o.xer_ov.ok):
 372             return
 373         if xer_out or (oe and oe_ok):
 374             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 375
 376     def get_xer_ca(res, alu, dec2):
 377         cry_out = yield dec2.e.do.output_carry
 378         xer_out = yield dec2.e.xer_out
 379         if not (yield alu.n.data_o.xer_ca.ok):
 380             return
 381         if xer_out or (cry_out):
 382             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 383
 384     def get_sim_int_o(res, sim, dec2):
 385         out_reg_valid = yield dec2.e.write_reg.ok
 386         if out_reg_valid:
 387             write_reg_idx = yield dec2.e.write_reg.data
 388             res['o'] = sim.gpr(write_reg_idx).value
 389
 390     def get_sim_int_o1(res, sim, dec2):
 391         out_reg_valid = yield dec2.e.write_ea.ok
 392         if out_reg_valid:
 393             write_reg_idx = yield dec2.e.write_ea.data
 394             res['o1'] = sim.gpr(write_reg_idx).value
 395
 396     def get_wr_sim_cr_a(res, sim, dec2):
 397         cridx_ok = yield dec2.e.write_cr.ok
 398         if cridx_ok:
 399             cridx = yield dec2.e.write_cr.data
 400             res['cr_a'] = sim.crl[cridx].get_range().value
 401
 402     def get_wr_fast_spr2(res, sim, dec2):
 403         ok = yield dec2.e.write_fast2.ok
 404         if ok:
 405             spr_num = yield dec2.e.write_fast2.data
 406             spr_num = fast_reg_to_spr(spr_num)
 407             spr_name = spr_dict[spr_num].SPR
 408             res['fast2'] = sim.spr[spr_name].value
 409
 410     def get_wr_fast_spr1(res, sim, dec2):
 411         ok = yield dec2.e.write_fast1.ok
 412         if ok:
 413             spr_num = yield dec2.e.write_fast1.data
 414             spr_num = fast_reg_to_spr(spr_num)
 415             spr_name = spr_dict[spr_num].SPR
 416             res['fast1'] = sim.spr[spr_name].value
 417
 418     def get_wr_slow_spr1(res, sim, dec2):
 419         ok = yield dec2.e.write_spr.ok
 420         if ok:
 421             spr_num = yield dec2.e.write_spr.data
 422             spr_num = slow_reg_to_spr(spr_num)
 423             spr_name = spr_dict[spr_num].SPR
 424             res['spr1'] = sim.spr[spr_name].value
 425
 426     def get_wr_sim_xer_ca(res, sim, dec2):
 427         # if not (yield alu.n.data_o.xer_ca.ok):
 428         #    return
 429         cry_out = yield dec2.e.do.output_carry
 430         xer_out = yield dec2.e.xer_out
 431         if cry_out or xer_out:
 432             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 433             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 434             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 435
 436     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 437         oe = yield dec2.e.do.oe.oe
 438         oe_ok = yield dec2.e.do.oe.ok
 439         xer_out = yield dec2.e.xer_out
 440         print("get_wr_sim_xer_ov", xer_out)
 441         if not (yield alu.n.data_o.xer_ov.ok):
 442             return
 443         if xer_out or (oe and oe_ok):
 444             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 445             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 446             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 447
 448     def get_wr_sim_xer_so(res, sim, alu, dec2):
 449         oe = yield dec2.e.do.oe.oe
 450         oe_ok = yield dec2.e.do.oe.ok
 451         xer_out = yield dec2.e.xer_out
 452         if not (yield alu.n.data_o.xer_so.ok):
 453             return
 454         if xer_out or (oe and oe_ok):
 455             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 456
 457     def get_sim_xer_ov(res, sim, dec2):
 458         oe = yield dec2.e.do.oe.oe
 459         oe_ok = yield dec2.e.do.oe.ok
 460         xer_in = yield dec2.e.xer_in
 461         print("get_sim_xer_ov", xer_in)
 462         if (xer_in & (1<<XERRegs.OV)) or (oe and oe_ok):
 463             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 464             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 465             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 466
 467     def get_sim_xer_so(res, sim, dec2):
 468         print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
 469         oe = yield dec2.e.do.oe.oe
 470         oe_ok = yield dec2.e.do.oe.ok
 471         xer_in = yield dec2.e.xer_in
 472         rc = yield dec2.e.do.rc.rc
 473         rc_ok = yield dec2.e.do.rc.ok
 474         if (xer_in & (1<<XERRegs.SO)) or (oe and oe_ok) or (rc and rc_ok):
 475             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 476
 477     def check_slow_spr1(dut, res, sim_o, msg):
 478         if 'spr1' in res:
 479             expected = sim_o['spr1']
 480             alu_out = res['spr1']
 481             print(f"expected {expected:x}, actual: {alu_out:x}")
 482             dut.assertEqual(expected, alu_out, msg)
 483
 484     def check_fast_spr1(dut, res, sim_o, msg):
 485         if 'fast1' in res:
 486             expected = sim_o['fast1']
 487             alu_out = res['fast1']
 488             print(f"expected {expected:x}, actual: {alu_out:x}")
 489             dut.assertEqual(expected, alu_out, msg)
 490
 491     def check_fast_spr2(dut, res, sim_o, msg):
 492         if 'fast2' in res:
 493             expected = sim_o['fast2']
 494             alu_out = res['fast2']
 495             print(f"expected {expected:x}, actual: {alu_out:x}")
 496             dut.assertEqual(expected, alu_out, msg)
 497
 498     def check_int_o1(dut, res, sim_o, msg):
 499         if 'o1' in res:
 500             expected = sim_o['o1']
 501             alu_out = res['o1']
 502             print(f"expected {expected:x}, actual: {alu_out:x}")
 503             dut.assertEqual(expected, alu_out, msg)
 504
 505     def check_int_o(dut, res, sim_o, msg):
 506         if 'o' in res:
 507             expected = sim_o['o']
 508             alu_out = res['o']
 509             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 510             dut.assertEqual(expected, alu_out, msg)
 511
 512     def check_msr(dut, res, sim_o, msg):
 513         if 'msr' in res:
 514             expected = sim_o['msr']
 515             alu_out = res['msr']
 516             print(f"expected {expected:x}, actual: {alu_out:x}")
 517             dut.assertEqual(expected, alu_out, msg)
 518
 519     def check_nia(dut, res, sim_o, msg):
 520         if 'nia' in res:
 521             expected = sim_o['nia']
 522             alu_out = res['nia']
 523             print(f"expected {expected:x}, actual: {alu_out:x}")
 524             dut.assertEqual(expected, alu_out, msg)
 525
 526     def check_cr_a(dut, res, sim_o, msg):
 527         if 'cr_a' in res:
 528             cr_expected = sim_o['cr_a']
 529             cr_actual = res['cr_a']
 530             print("CR", cr_expected, cr_actual)
 531             dut.assertEqual(cr_expected, cr_actual, msg)
 532
 533     def check_xer_ca(dut, res, sim_o, msg):
 534         if 'xer_ca' in res:
 535             ca_expected = sim_o['xer_ca']
 536             ca_actual = res['xer_ca']
 537             print("CA", ca_expected, ca_actual)
 538             dut.assertEqual(ca_expected, ca_actual, msg)
 539
 540     def check_xer_ov(dut, res, sim_o, msg):
 541         if 'xer_ov' in res:
 542             ov_expected = sim_o['xer_ov']
 543             ov_actual = res['xer_ov']
 544             print("OV", ov_expected, ov_actual)
 545             dut.assertEqual(ov_expected, ov_actual, msg)
 546
 547     def check_xer_so(dut, res, sim_o, msg):
 548         if 'xer_so' in res:
 549             so_expected = sim_o['xer_so']
 550             so_actual = res['xer_so']
 551             print("SO", so_expected, so_actual)
 552             dut.assertEqual(so_expected, so_actual, msg)