3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
9 from soc
.decoder
.power_enums
import XER_bits
, CryIn
, spr_dict
10 from soc
.regfile
.util
import fast_reg_to_spr
, slow_reg_to_spr
# HACK!
11 from soc
.regfile
.regfiles
import XERRegs
, FastRegs
14 # TODO: make this a util routine (somewhere)
15 def mask_extend(x
, nbits
, repeat
):
17 extended
= (1<<repeat
)-1
18 for i
in range(nbits
):
20 res |
= extended
<< (i
*repeat
)
24 class SkipCase(Exception):
25 """Raise this exception to skip a test case.
27 Usually you'd use one of the skip_case* decorators.
29 For use with TestAccumulatorBase
34 """identity function"""
38 def skip_case(reason
):
40 Unconditionally skip a test case.
43 @skip_case("my reason for skipping")
51 For use with TestAccumulatorBase
54 assert not isinstance(item
, type), \
55 "can't use skip_case to decorate types"
57 @functools.wraps(item
)
58 def wrapper(*args
, **kwargs
):
59 raise SkipCase(reason
)
61 if isinstance(reason
, types
.FunctionType
):
64 return decorator(item
)
68 def skip_case_if(condition
, reason
):
70 Conditionally skip a test case.
73 @skip_case_if(should_i_skip(), "my reason for skipping")
77 For use with TestAccumulatorBase
80 return skip_case(reason
)
84 class TestAccumulatorBase
:
88 # automatically identifies anything starting with "case_" and
89 # runs it. very similar to unittest auto-identification except
90 # we need a different system
91 for n
, v
in self
.__class
__.__dict
__.items():
92 if n
.startswith("case_") and callable(v
):
96 # TODO(programmerjake): translate to final test sending
97 # skip signal to unittest. for now, just print the skipped
99 print(f
"SKIPPED({n}):", str(e
))
101 def add_case(self
, prog
, initial_regs
=None, initial_sprs
=None,
102 initial_cr
=0, initial_msr
=0,
105 test_name
= inspect
.stack()[1][3] # name of caller of this function
106 tc
= TestCase(prog
, test_name
,
107 regs
=initial_regs
, sprs
=initial_sprs
, cr
=initial_cr
,
111 self
.test_data
.append(tc
)
115 def __init__(self
, program
, name
, regs
=None, sprs
=None, cr
=0, mem
=None,
118 extra_break_addr
=None):
120 self
.program
= program
135 self
.extra_break_addr
= extra_break_addr
140 def get_sim_fast_reg(res
, sim
, dec2
, reg
, name
):
141 spr_sel
= fast_reg_to_spr(reg
)
142 spr_data
= sim
.spr
[spr_sel
].value
145 def get_sim_cia(res
, sim
, dec2
):
146 res
['cia'] = sim
.pc
.CIA
.value
148 # use this *after* the simulation has run a step (it returns CIA)
149 def get_sim_nia(res
, sim
, dec2
):
150 res
['nia'] = sim
.pc
.CIA
.value
152 def get_sim_msr(res
, sim
, dec2
):
153 res
['msr'] = sim
.msr
.value
155 def get_sim_slow_spr1(res
, sim
, dec2
):
156 spr1_en
= yield dec2
.e
.read_spr1
.ok
158 spr1_sel
= yield dec2
.e
.read_spr1
.data
159 spr1_sel
= slow_reg_to_spr(spr1_sel
)
160 spr1_data
= sim
.spr
[spr1_sel
].value
161 res
['spr1'] = spr1_data
163 def get_sim_fast_spr1(res
, sim
, dec2
):
164 fast1_en
= yield dec2
.e
.read_fast1
.ok
166 fast1_sel
= yield dec2
.e
.read_fast1
.data
167 spr1_sel
= fast_reg_to_spr(fast1_sel
)
168 spr1_data
= sim
.spr
[spr1_sel
].value
169 res
['fast1'] = spr1_data
171 def get_sim_fast_spr2(res
, sim
, dec2
):
172 fast2_en
= yield dec2
.e
.read_fast2
.ok
174 fast2_sel
= yield dec2
.e
.read_fast2
.data
175 spr2_sel
= fast_reg_to_spr(fast2_sel
)
176 spr2_data
= sim
.spr
[spr2_sel
].value
177 res
['fast2'] = spr2_data
179 def get_sim_cr_a(res
, sim
, dec2
):
180 cridx_ok
= yield dec2
.e
.read_cr1
.ok
182 cridx
= yield dec2
.e
.read_cr1
.data
183 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
185 def get_sim_cr_b(res
, sim
, dec2
):
186 cridx_ok
= yield dec2
.e
.read_cr2
.ok
188 cridx
= yield dec2
.e
.read_cr2
.data
189 res
['cr_b'] = sim
.crl
[cridx
].get_range().value
191 def get_sim_cr_c(res
, sim
, dec2
):
192 cridx_ok
= yield dec2
.e
.read_cr3
.ok
194 cridx
= yield dec2
.e
.read_cr3
.data
195 res
['cr_c'] = sim
.crl
[cridx
].get_range().value
197 def get_sim_int_ra(res
, sim
, dec2
):
198 # TODO: immediate RA zero
199 reg1_ok
= yield dec2
.e
.read_reg1
.ok
201 data1
= yield dec2
.e
.read_reg1
.data
202 res
['ra'] = sim
.gpr(data1
).value
204 def get_sim_int_rb(res
, sim
, dec2
):
205 reg2_ok
= yield dec2
.e
.read_reg2
.ok
207 data
= yield dec2
.e
.read_reg2
.data
208 res
['rb'] = sim
.gpr(data
).value
210 def get_sim_int_rc(res
, sim
, dec2
):
211 reg3_ok
= yield dec2
.e
.read_reg3
.ok
213 data
= yield dec2
.e
.read_reg3
.data
214 res
['rc'] = sim
.gpr(data
).value
216 def get_rd_sim_xer_ca(res
, sim
, dec2
):
217 cry_in
= yield dec2
.e
.do
.input_carry
218 xer_in
= yield dec2
.e
.xer_in
219 if (xer_in
& (1<<XERRegs
.CA
)) or cry_in
== CryIn
.CA
.value
:
220 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
221 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
222 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
224 def set_int_ra(alu
, dec2
, inp
):
225 # TODO: immediate RA zero.
227 yield alu
.p
.data_i
.ra
.eq(inp
['ra'])
229 yield alu
.p
.data_i
.ra
.eq(0)
231 def set_int_rb(alu
, dec2
, inp
):
232 yield alu
.p
.data_i
.rb
.eq(0)
234 yield alu
.p
.data_i
.rb
.eq(inp
['rb'])
235 # If there's an immediate, set the B operand to that
236 imm_ok
= yield dec2
.e
.do
.imm_data
.ok
238 data2
= yield dec2
.e
.do
.imm_data
.data
239 yield alu
.p
.data_i
.rb
.eq(data2
)
241 def set_int_rc(alu
, dec2
, inp
):
243 yield alu
.p
.data_i
.rc
.eq(inp
['rc'])
245 yield alu
.p
.data_i
.rc
.eq(0)
247 def set_xer_ca(alu
, dec2
, inp
):
249 yield alu
.p
.data_i
.xer_ca
.eq(inp
['xer_ca'])
250 print("extra inputs: CA/32", bin(inp
['xer_ca']))
252 def set_xer_ov(alu
, dec2
, inp
):
254 yield alu
.p
.data_i
.xer_ov
.eq(inp
['xer_ov'])
255 print("extra inputs: OV/32", bin(inp
['xer_ov']))
257 def set_xer_so(alu
, dec2
, inp
):
260 print("extra inputs: so", so
)
261 yield alu
.p
.data_i
.xer_so
.eq(so
)
263 def set_msr(alu
, dec2
, inp
):
264 print("TODO: deprecate set_msr")
266 yield alu
.p
.data_i
.msr
.eq(inp
['msr'])
268 def set_cia(alu
, dec2
, inp
):
269 print("TODO: deprecate set_cia")
271 yield alu
.p
.data_i
.cia
.eq(inp
['cia'])
273 def set_slow_spr1(alu
, dec2
, inp
):
275 yield alu
.p
.data_i
.spr1
.eq(inp
['spr1'])
277 def set_slow_spr2(alu
, dec2
, inp
):
279 yield alu
.p
.data_i
.spr2
.eq(inp
['spr2'])
281 def set_fast_spr1(alu
, dec2
, inp
):
283 yield alu
.p
.data_i
.fast1
.eq(inp
['fast1'])
285 def set_fast_spr2(alu
, dec2
, inp
):
287 yield alu
.p
.data_i
.fast2
.eq(inp
['fast2'])
289 def set_cr_a(alu
, dec2
, inp
):
291 yield alu
.p
.data_i
.cr_a
.eq(inp
['cr_a'])
293 def set_cr_b(alu
, dec2
, inp
):
295 yield alu
.p
.data_i
.cr_b
.eq(inp
['cr_b'])
297 def set_cr_c(alu
, dec2
, inp
):
299 yield alu
.p
.data_i
.cr_c
.eq(inp
['cr_c'])
301 def set_full_cr(alu
, dec2
, inp
):
303 full_reg
= yield dec2
.e
.do
.read_cr_whole
.data
304 full_reg_ok
= yield dec2
.e
.do
.read_cr_whole
.ok
305 full_cr_mask
= mask_extend(full_reg
, 8, 4)
306 yield alu
.p
.data_i
.full_cr
.eq(inp
['full_cr'] & full_cr_mask
)
308 yield alu
.p
.data_i
.full_cr
.eq(0)
310 def get_slow_spr1(res
, alu
, dec2
):
311 spr1_valid
= yield alu
.n
.data_o
.spr1
.ok
313 res
['spr1'] = yield alu
.n
.data_o
.spr1
.data
315 def get_slow_spr2(res
, alu
, dec2
):
316 spr2_valid
= yield alu
.n
.data_o
.spr2
.ok
318 res
['spr2'] = yield alu
.n
.data_o
.spr2
.data
320 def get_fast_spr1(res
, alu
, dec2
):
321 spr1_valid
= yield alu
.n
.data_o
.fast1
.ok
323 res
['fast1'] = yield alu
.n
.data_o
.fast1
.data
325 def get_fast_spr2(res
, alu
, dec2
):
326 spr2_valid
= yield alu
.n
.data_o
.fast2
.ok
328 res
['fast2'] = yield alu
.n
.data_o
.fast2
.data
330 def get_cia(res
, alu
, dec2
):
331 res
['cia'] = yield alu
.p
.data_i
.cia
333 def get_nia(res
, alu
, dec2
):
334 nia_valid
= yield alu
.n
.data_o
.nia
.ok
336 res
['nia'] = yield alu
.n
.data_o
.nia
.data
338 def get_msr(res
, alu
, dec2
):
339 msr_valid
= yield alu
.n
.data_o
.msr
.ok
341 res
['msr'] = yield alu
.n
.data_o
.msr
.data
343 def get_int_o1(res
, alu
, dec2
):
344 out_reg_valid
= yield dec2
.e
.write_ea
.ok
346 res
['o1'] = yield alu
.n
.data_o
.o1
.data
348 def get_int_o(res
, alu
, dec2
):
349 out_reg_valid
= yield dec2
.e
.write_reg
.ok
351 res
['o'] = yield alu
.n
.data_o
.o
.data
353 def get_cr_a(res
, alu
, dec2
):
354 cridx_ok
= yield dec2
.e
.write_cr
.ok
356 res
['cr_a'] = yield alu
.n
.data_o
.cr0
.data
358 def get_xer_so(res
, alu
, dec2
):
359 oe
= yield dec2
.e
.do
.oe
.oe
360 oe_ok
= yield dec2
.e
.do
.oe
.ok
361 xer_out
= yield dec2
.e
.xer_out
362 if not (yield alu
.n
.data_o
.xer_so
.ok
):
364 if xer_out
or (oe
and oe_ok
):
365 res
['xer_so'] = yield alu
.n
.data_o
.xer_so
.data
[0]
367 def get_xer_ov(res
, alu
, dec2
):
368 oe
= yield dec2
.e
.do
.oe
.oe
369 oe_ok
= yield dec2
.e
.do
.oe
.ok
370 xer_out
= yield dec2
.e
.xer_out
371 if not (yield alu
.n
.data_o
.xer_ov
.ok
):
373 if xer_out
or (oe
and oe_ok
):
374 res
['xer_ov'] = yield alu
.n
.data_o
.xer_ov
.data
376 def get_xer_ca(res
, alu
, dec2
):
377 cry_out
= yield dec2
.e
.do
.output_carry
378 xer_out
= yield dec2
.e
.xer_out
379 if not (yield alu
.n
.data_o
.xer_ca
.ok
):
381 if xer_out
or (cry_out
):
382 res
['xer_ca'] = yield alu
.n
.data_o
.xer_ca
.data
384 def get_sim_int_o(res
, sim
, dec2
):
385 out_reg_valid
= yield dec2
.e
.write_reg
.ok
387 write_reg_idx
= yield dec2
.e
.write_reg
.data
388 res
['o'] = sim
.gpr(write_reg_idx
).value
390 def get_sim_int_o1(res
, sim
, dec2
):
391 out_reg_valid
= yield dec2
.e
.write_ea
.ok
393 write_reg_idx
= yield dec2
.e
.write_ea
.data
394 res
['o1'] = sim
.gpr(write_reg_idx
).value
396 def get_wr_sim_cr_a(res
, sim
, dec2
):
397 cridx_ok
= yield dec2
.e
.write_cr
.ok
399 cridx
= yield dec2
.e
.write_cr
.data
400 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
402 def get_wr_fast_spr2(res
, sim
, dec2
):
403 ok
= yield dec2
.e
.write_fast2
.ok
405 spr_num
= yield dec2
.e
.write_fast2
.data
406 spr_num
= fast_reg_to_spr(spr_num
)
407 spr_name
= spr_dict
[spr_num
].SPR
408 res
['fast2'] = sim
.spr
[spr_name
].value
410 def get_wr_fast_spr1(res
, sim
, dec2
):
411 ok
= yield dec2
.e
.write_fast1
.ok
413 spr_num
= yield dec2
.e
.write_fast1
.data
414 spr_num
= fast_reg_to_spr(spr_num
)
415 spr_name
= spr_dict
[spr_num
].SPR
416 res
['fast1'] = sim
.spr
[spr_name
].value
418 def get_wr_slow_spr1(res
, sim
, dec2
):
419 ok
= yield dec2
.e
.write_spr
.ok
421 spr_num
= yield dec2
.e
.write_spr
.data
422 spr_num
= slow_reg_to_spr(spr_num
)
423 spr_name
= spr_dict
[spr_num
].SPR
424 res
['spr1'] = sim
.spr
[spr_name
].value
426 def get_wr_sim_xer_ca(res
, sim
, dec2
):
427 # if not (yield alu.n.data_o.xer_ca.ok):
429 cry_out
= yield dec2
.e
.do
.output_carry
430 xer_out
= yield dec2
.e
.xer_out
431 if cry_out
or xer_out
:
432 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
433 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
434 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
436 def get_wr_sim_xer_ov(res
, sim
, alu
, dec2
):
437 oe
= yield dec2
.e
.do
.oe
.oe
438 oe_ok
= yield dec2
.e
.do
.oe
.ok
439 xer_out
= yield dec2
.e
.xer_out
440 print("get_wr_sim_xer_ov", xer_out
)
441 if not (yield alu
.n
.data_o
.xer_ov
.ok
):
443 if xer_out
or (oe
and oe_ok
):
444 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
445 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
446 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
448 def get_wr_sim_xer_so(res
, sim
, alu
, dec2
):
449 oe
= yield dec2
.e
.do
.oe
.oe
450 oe_ok
= yield dec2
.e
.do
.oe
.ok
451 xer_out
= yield dec2
.e
.xer_out
452 if not (yield alu
.n
.data_o
.xer_so
.ok
):
454 if xer_out
or (oe
and oe_ok
):
455 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
457 def get_sim_xer_ov(res
, sim
, dec2
):
458 oe
= yield dec2
.e
.do
.oe
.oe
459 oe_ok
= yield dec2
.e
.do
.oe
.ok
460 xer_in
= yield dec2
.e
.xer_in
461 print("get_sim_xer_ov", xer_in
)
462 if (xer_in
& (1<<XERRegs
.OV
)) or (oe
and oe_ok
):
463 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
464 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
465 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
467 def get_sim_xer_so(res
, sim
, dec2
):
468 print ("XER", sim
.spr
.__class
__, sim
.spr
, sim
.spr
['XER'])
469 oe
= yield dec2
.e
.do
.oe
.oe
470 oe_ok
= yield dec2
.e
.do
.oe
.ok
471 xer_in
= yield dec2
.e
.xer_in
472 rc
= yield dec2
.e
.do
.rc
.rc
473 rc_ok
= yield dec2
.e
.do
.rc
.ok
474 if (xer_in
& (1<<XERRegs
.SO
)) or (oe
and oe_ok
) or (rc
and rc_ok
):
475 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
477 def check_slow_spr1(dut
, res
, sim_o
, msg
):
479 expected
= sim_o
['spr1']
480 alu_out
= res
['spr1']
481 print(f
"expected {expected:x}, actual: {alu_out:x}")
482 dut
.assertEqual(expected
, alu_out
, msg
)
484 def check_fast_spr1(dut
, res
, sim_o
, msg
):
486 expected
= sim_o
['fast1']
487 alu_out
= res
['fast1']
488 print(f
"expected {expected:x}, actual: {alu_out:x}")
489 dut
.assertEqual(expected
, alu_out
, msg
)
491 def check_fast_spr2(dut
, res
, sim_o
, msg
):
493 expected
= sim_o
['fast2']
494 alu_out
= res
['fast2']
495 print(f
"expected {expected:x}, actual: {alu_out:x}")
496 dut
.assertEqual(expected
, alu_out
, msg
)
498 def check_int_o1(dut
, res
, sim_o
, msg
):
500 expected
= sim_o
['o1']
502 print(f
"expected {expected:x}, actual: {alu_out:x}")
503 dut
.assertEqual(expected
, alu_out
, msg
)
505 def check_int_o(dut
, res
, sim_o
, msg
):
507 expected
= sim_o
['o']
509 print(f
"expected int sim {expected:x}, actual: {alu_out:x}")
510 dut
.assertEqual(expected
, alu_out
, msg
)
512 def check_msr(dut
, res
, sim_o
, msg
):
514 expected
= sim_o
['msr']
516 print(f
"expected {expected:x}, actual: {alu_out:x}")
517 dut
.assertEqual(expected
, alu_out
, msg
)
519 def check_nia(dut
, res
, sim_o
, msg
):
521 expected
= sim_o
['nia']
523 print(f
"expected {expected:x}, actual: {alu_out:x}")
524 dut
.assertEqual(expected
, alu_out
, msg
)
526 def check_cr_a(dut
, res
, sim_o
, msg
):
528 cr_expected
= sim_o
['cr_a']
529 cr_actual
= res
['cr_a']
530 print("CR", cr_expected
, cr_actual
)
531 dut
.assertEqual(cr_expected
, cr_actual
, msg
)
533 def check_xer_ca(dut
, res
, sim_o
, msg
):
535 ca_expected
= sim_o
['xer_ca']
536 ca_actual
= res
['xer_ca']
537 print("CA", ca_expected
, ca_actual
)
538 dut
.assertEqual(ca_expected
, ca_actual
, msg
)
540 def check_xer_ov(dut
, res
, sim_o
, msg
):
542 ov_expected
= sim_o
['xer_ov']
543 ov_actual
= res
['xer_ov']
544 print("OV", ov_expected
, ov_actual
)
545 dut
.assertEqual(ov_expected
, ov_actual
, msg
)
547 def check_xer_so(dut
, res
, sim_o
, msg
):
549 so_expected
= sim_o
['xer_so']
550 so_actual
= res
['xer_so']
551 print("SO", so_expected
, so_actual
)
552 dut
.assertEqual(so_expected
, so_actual
, msg
)