3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
6 from soc
.decoder
.power_enums
import XER_bits
, CryIn
, spr_dict
7 from soc
.regfile
.util
import fast_reg_to_spr
# HACK!
8 from soc
.regfile
.regfiles
import FastRegs
12 def __init__(self
, program
, name
, regs
=None, sprs
=None, cr
=0, mem
=None,
15 self
.program
= program
32 def get_sim_fast_reg(res
, sim
, dec2
, reg
, name
):
33 spr_sel
= fast_reg_to_spr(reg
)
34 spr_data
= sim
.spr
[spr_sel
].value
37 def get_sim_cia(res
, sim
, dec2
):
38 return self
.get_sim_fast_reg(res
, sim
, dec2
, FastRegs
.PC
, 'pc')
40 def get_sim_msr(res
, sim
, dec2
):
41 return self
.get_sim_fast_reg(res
, sim
, dec2
, FastRegs
.MSR
, 'msr')
43 def get_sim_fast_spr1(res
, sim
, dec2
):
44 fast1_en
= yield dec2
.e
.read_fast1
.ok
46 fast1_sel
= yield dec2
.e
.read_fast1
.data
47 spr1_sel
= fast_reg_to_spr(fast1_sel
)
48 spr1_data
= sim
.spr
[spr1_sel
].value
49 res
['spr1'] = spr1_data
51 def get_sim_fast_spr2(res
, sim
, dec2
):
52 fast2_en
= yield dec2
.e
.read_fast2
.ok
54 fast2_sel
= yield dec2
.e
.read_fast2
.data
55 spr2_sel
= fast_reg_to_spr(fast2_sel
)
56 spr2_data
= sim
.spr
[spr2_sel
].value
57 res
['spr2'] = spr2_data
59 def get_sim_cr_a(res
, sim
, dec2
):
60 cridx_ok
= yield dec2
.e
.read_cr1
.ok
62 cridx
= yield dec2
.e
.read_cr1
.data
63 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
65 def get_sim_int_ra(res
, sim
, dec2
):
66 # TODO: immediate RA zero
67 reg1_ok
= yield dec2
.e
.read_reg1
.ok
69 data1
= yield dec2
.e
.read_reg1
.data
70 res
['ra'] = sim
.gpr(data1
).value
72 def get_sim_int_rb(res
, sim
, dec2
):
73 reg2_ok
= yield dec2
.e
.read_reg2
.ok
75 data
= yield dec2
.e
.read_reg2
.data
76 res
['rb'] = sim
.gpr(data
).value
78 def get_sim_int_rc(res
, sim
, dec2
):
79 reg3_ok
= yield dec2
.e
.read_reg3
.ok
81 data
= yield dec2
.e
.read_reg3
.data
82 res
['rc'] = sim
.gpr(data
).value
84 def get_rd_sim_xer_ca(res
, sim
, dec2
):
85 cry_in
= yield dec2
.e
.input_carry
86 if cry_in
== CryIn
.CA
.value
:
87 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
88 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
89 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
91 def set_int_ra(alu
, dec2
, inp
):
92 # TODO: immediate RA zero.
94 yield alu
.p
.data_i
.ra
.eq(inp
['ra'])
96 yield alu
.p
.data_i
.ra
.eq(0)
98 def set_int_rb(alu
, dec2
, inp
):
99 yield alu
.p
.data_i
.rb
.eq(0)
101 yield alu
.p
.data_i
.rb
.eq(inp
['rb'])
102 # If there's an immediate, set the B operand to that
103 imm_ok
= yield dec2
.e
.imm_data
.imm_ok
105 data2
= yield dec2
.e
.imm_data
.imm
106 yield alu
.p
.data_i
.rb
.eq(data2
)
108 def set_int_rc(alu
, dec2
, inp
):
110 yield alu
.p
.data_i
.rc
.eq(inp
['rc'])
112 yield alu
.p
.data_i
.rc
.eq(0)
114 def set_xer_ca(alu
, dec2
, inp
):
116 yield alu
.p
.data_i
.xer_ca
.eq(inp
['xer_ca'])
117 print ("extra inputs: CA/32", bin(inp
['xer_ca']))
119 def set_xer_so(alu
, dec2
, inp
):
122 print ("extra inputs: so", so
)
123 yield alu
.p
.data_i
.xer_so
.eq(so
)
125 def set_fast_msr(alu
, dec2
, inp
):
127 yield alu
.p
.data_i
.msr
.eq(inp
['msr'])
129 def set_fast_cia(alu
, dec2
, inp
):
131 yield alu
.p
.data_i
.cia
.eq(inp
['cia'])
133 def set_fast_spr1(alu
, dec2
, inp
):
135 yield alu
.p
.data_i
.spr1
.eq(inp
['spr1'])
137 def set_fast_spr2(alu
, dec2
, inp
):
139 yield alu
.p
.data_i
.spr2
.eq(inp
['spr2'])
141 def set_cr_a(alu
, dec2
, inp
):
143 yield alu
.p
.data_i
.cr_a
.eq(inp
['cr_a'])
145 def set_cr_b(alu
, dec2
, inp
):
147 yield alu
.p
.data_i
.cr_b
.eq(inp
['cr_b'])
149 def set_cr_c(alu
, dec2
, inp
):
151 yield alu
.p
.data_i
.cr_c
.eq(inp
['cr_c'])
153 def set_full_cr(alu
, dec2
, inp
):
155 yield alu
.p
.data_i
.full_cr
.eq(inp
['full_cr'])
157 yield alu
.p
.data_i
.full_cr
.eq(0)
159 def get_fast_spr1(res
, alu
, dec2
):
160 spr1_valid
= yield alu
.n
.data_o
.spr1
.ok
162 res
['spr1'] = yield alu
.n
.data_o
.spr1
.data
164 def get_fast_spr2(res
, alu
, dec2
):
165 spr2_valid
= yield alu
.n
.data_o
.spr2
.ok
167 res
['spr2'] = yield alu
.n
.data_o
.spr2
.data
169 def get_fast_nia(res
, alu
, dec2
):
170 nia_valid
= yield alu
.n
.data_o
.nia
.ok
172 res
['nia'] = yield alu
.n
.data_o
.nia
.data
174 def get_fast_msr(res
, alu
, dec2
):
175 msr_valid
= yield alu
.n
.data_o
.msr
.ok
177 res
['msr'] = yield alu
.n
.data_o
.msr
.data
179 def get_int_o1(res
, alu
, dec2
):
180 out_reg_valid
= yield dec2
.e
.write_ea
.ok
182 res
['o1'] = yield alu
.n
.data_o
.o1
.data
184 def get_int_o(res
, alu
, dec2
):
185 out_reg_valid
= yield dec2
.e
.write_reg
.ok
187 res
['o'] = yield alu
.n
.data_o
.o
.data
189 def get_cr_a(res
, alu
, dec2
):
190 cridx_ok
= yield dec2
.e
.write_cr
.ok
192 res
['cr_a'] = yield alu
.n
.data_o
.cr0
.data
194 def get_xer_so(res
, alu
, dec2
):
195 oe
= yield dec2
.e
.oe
.oe
196 oe_ok
= yield dec2
.e
.oe
.ok
198 res
['xer_so'] = yield alu
.n
.data_o
.xer_so
.data
[0]
200 def get_xer_ov(res
, alu
, dec2
):
201 oe
= yield dec2
.e
.oe
.oe
202 oe_ok
= yield dec2
.e
.oe
.ok
204 res
['xer_ov'] = yield alu
.n
.data_o
.xer_ov
.data
206 def get_xer_ca(res
, alu
, dec2
):
207 cry_out
= yield dec2
.e
.output_carry
209 res
['xer_ca'] = yield alu
.n
.data_o
.xer_ca
.data
211 def get_sim_int_o(res
, sim
, dec2
):
212 out_reg_valid
= yield dec2
.e
.write_reg
.ok
214 write_reg_idx
= yield dec2
.e
.write_reg
.data
215 res
['o'] = sim
.gpr(write_reg_idx
).value
217 def get_sim_int_o1(res
, sim
, dec2
):
218 out_reg_valid
= yield dec2
.e
.write_ea
.ok
220 write_reg_idx
= yield dec2
.e
.write_ea
.data
221 res
['o1'] = sim
.gpr(write_reg_idx
).value
223 def get_wr_sim_cr_a(res
, sim
, dec2
):
224 cridx_ok
= yield dec2
.e
.write_cr
.ok
226 cridx
= yield dec2
.e
.write_cr
.data
227 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
229 def get_wr_fast_spr2(res
, sim
, dec2
):
230 ok
= yield dec2
.e
.write_fast2
.ok
232 spr_num
= yield dec2
.e
.write_fast2
.data
233 spr_name
= spr_dict
[spr_num
]
234 res
['spr2'] = sim
.spr
[spr_name
]
236 def get_wr_fast_spr1(res
, sim
, dec2
):
237 ok
= yield dec2
.e
.write_fast1
.ok
239 spr_num
= yield dec2
.e
.write_fast1
.data
240 spr_name
= spr_dict
[spr_num
]
241 res
['spr1'] = sim
.spr
[spr_name
]
243 def get_wr_sim_xer_ca(res
, sim
, dec2
):
244 cry_out
= yield dec2
.e
.output_carry
246 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
247 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
248 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
250 def get_sim_xer_ov(res
, sim
, dec2
):
251 oe
= yield dec2
.e
.oe
.oe
252 oe_ok
= yield dec2
.e
.oe
.ok
254 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
255 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
256 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
258 def get_sim_xer_so(res
, sim
, dec2
):
259 oe
= yield dec2
.e
.oe
.oe
260 oe_ok
= yield dec2
.e
.oe
.ok
262 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
264 def check_int_o1(dut
, res
, sim_o
, msg
):
266 expected
= sim_o
['o1']
268 print(f
"expected {expected:x}, actual: {alu_out:x}")
269 dut
.assertEqual(expected
, alu_out
, msg
)
271 def check_int_o(dut
, res
, sim_o
, msg
):
273 expected
= sim_o
['o']
275 print(f
"expected {expected:x}, actual: {alu_out:x}")
276 dut
.assertEqual(expected
, alu_out
, msg
)
278 def check_cr_a(dut
, res
, sim_o
, msg
):
280 cr_expected
= sim_o
['cr_a']
281 cr_actual
= res
['cr_a']
282 print ("CR", cr_expected
, cr_actual
)
283 dut
.assertEqual(cr_expected
, cr_actual
, msg
)
285 def check_xer_ca(dut
, res
, sim_o
, msg
):
287 ca_expected
= sim_o
['xer_ca']
288 ca_actual
= res
['xer_ca']
289 print ("CA", ca_expected
, ca_actual
)
290 dut
.assertEqual(ca_expected
, ca_actual
, msg
)
292 def check_xer_ov(dut
, res
, sim_o
, msg
):
294 ov_expected
= sim_o
['xer_ov']
295 ov_actual
= res
['xer_ov']
296 print ("OV", ov_expected
, ov_actual
)
297 dut
.assertEqual(ov_expected
, ov_actual
, msg
)
299 def check_xer_so(dut
, res
, sim_o
, msg
):
301 so_expected
= sim_o
['xer_so']
302 so_actual
= res
['xer_so']
303 print ("SO", so_expected
, so_actual
)
304 dut
.assertEqual(so_expected
, so_actual
, msg
)