src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8
   9
  10 class TestCase:
  11     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  12                        msr=0):
  13
  14         self.program = program
  15         self.name = name
  16
  17         if regs is None:
  18             regs = [0] * 32
  19         if sprs is None:
  20             sprs = {}
  21         if mem is None:
  22             mem = {}
  23         self.regs = regs
  24         self.sprs = sprs
  25         self.cr = cr
  26         self.mem = mem
  27         self.msr = msr
  28
  29 class ALUHelpers:
  30
  31     def get_sim_fast_spr1(res, sim, dec2):
  32         fast1_en = yield dec2.e.read_fast1.ok
  33         if fast1_en:
  34             fast1_sel = yield dec2.e.read_fast1.data
  35             spr1_sel = fast_reg_to_spr(fast1_sel)
  36             spr1_data = sim.spr[spr1_sel].value
  37             res['spr1'] = spr1_data
  38
  39     def get_sim_fast_spr2(res, sim, dec2):
  40         fast2_en = yield dec2.e.read_fast2.ok
  41         if fast2_en:
  42             fast2_sel = yield dec2.e.read_fast2.data
  43             spr2_sel = fast_reg_to_spr(fast2_sel)
  44             spr2_data = sim.spr[spr2_sel].value
  45             res['spr2'] = spr2_data
  46
  47     def get_sim_cr_a(res, sim, dec2):
  48         cridx_ok = yield dec2.e.read_cr1.ok
  49         if cridx_ok:
  50             cridx = yield dec2.e.read_cr1.data
  51             res['cr_a'] = sim.crl[cridx].get_range().value
  52
  53     def get_sim_int_ra(res, sim, dec2):
  54         # TODO: immediate RA zero
  55         reg1_ok = yield dec2.e.read_reg1.ok
  56         if reg1_ok:
  57             data1 = yield dec2.e.read_reg1.data
  58             res['ra'] = sim.gpr(data1).value
  59
  60     def get_sim_int_rb(res, sim, dec2):
  61         reg2_ok = yield dec2.e.read_reg2.ok
  62         if reg2_ok:
  63             data = yield dec2.e.read_reg2.data
  64             res['rb'] = sim.gpr(data).value
  65
  66     def get_sim_int_rc(res, sim, dec2):
  67         reg3_ok = yield dec2.e.read_reg3.ok
  68         if reg3_ok:
  69             data = yield dec2.e.read_reg3.data
  70             res['rc'] = sim.gpr(data).value
  71
  72     def get_rd_sim_xer_ca(res, sim, dec2):
  73         cry_in = yield dec2.e.input_carry
  74         if cry_in:
  75             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  76             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  77             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
  78
  79     def set_int_ra(alu, dec2, inp):
  80         # TODO: immediate RA zero.
  81         if 'ra' in inp:
  82             yield alu.p.data_i.ra.eq(inp['ra'])
  83         else:
  84             yield alu.p.data_i.ra.eq(0)
  85
  86     def set_int_rb(alu, dec2, inp):
  87         yield alu.p.data_i.rb.eq(0)
  88         if 'rb' in inp:
  89             yield alu.p.data_i.rb.eq(inp['rb'])
  90         # If there's an immediate, set the B operand to that
  91         imm_ok = yield dec2.e.imm_data.imm_ok
  92         if imm_ok:
  93             data2 = yield dec2.e.imm_data.imm
  94             yield alu.p.data_i.rb.eq(data2)
  95
  96     def set_int_rc(alu, dec2, inp):
  97         if 'rc' in inp:
  98             yield alu.p.data_i.rc.eq(inp['rc'])
  99         else:
 100             yield alu.p.data_i.rc.eq(0)
 101
 102     def set_xer_ca(alu, dec2, inp):
 103         if 'xer_ca' in inp:
 104             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 105             print ("extra inputs: CA/32", bin(inp['xer_ca']))
 106
 107     def set_xer_so(alu, dec2, inp):
 108         if 'xer_so' in inp:
 109             so = inp['xer_so']
 110             print ("extra inputs: so", so)
 111             yield alu.p.data_i.xer_so.eq(so)
 112
 113     def set_fast_cia(alu, dec2, inp):
 114         if 'cia' in inp:
 115             yield alu.p.data_i.cia.eq(inp['cia'])
 116
 117     def set_fast_spr1(alu, dec2, inp):
 118         if 'spr1' in inp:
 119             yield alu.p.data_i.spr1.eq(inp['spr1'])
 120
 121     def set_fast_spr2(alu, dec2, inp):
 122         if 'spr2' in inp:
 123             yield alu.p.data_i.spr2.eq(inp['spr2'])
 124
 125     def set_cr_a(alu, dec2, inp):
 126         if 'cr_a' in inp:
 127             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 128
 129     def set_cr_b(alu, dec2, inp):
 130         if 'cr_b' in inp:
 131             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 132
 133     def set_cr_c(alu, dec2, inp):
 134         if 'cr_c' in inp:
 135             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 136
 137     def set_full_cr(alu, dec2, inp):
 138         if 'full_cr' in inp:
 139             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 140         else:
 141             yield alu.p.data_i.full_cr.eq(0)
 142
 143     def get_int_o(res, alu, dec2):
 144         out_reg_valid = yield dec2.e.write_reg.ok
 145         if out_reg_valid:
 146             res['o'] = yield alu.n.data_o.o.data
 147
 148     def get_cr_a(res, alu, dec2):
 149         cridx_ok = yield dec2.e.write_cr.ok
 150         if cridx_ok:
 151             res['cr_a'] = yield alu.n.data_o.cr0.data
 152
 153     def get_xer_so(res, alu, dec2):
 154         oe = yield dec2.e.oe.oe
 155         oe_ok = yield dec2.e.oe.ok
 156         if oe and oe_ok:
 157             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 158
 159     def get_xer_ov(res, alu, dec2):
 160         oe = yield dec2.e.oe.oe
 161         oe_ok = yield dec2.e.oe.ok
 162         if oe and oe_ok:
 163             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 164
 165     def get_xer_ca(res, alu, dec2):
 166         cry_out = yield dec2.e.output_carry
 167         if cry_out:
 168             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 169
 170     def get_sim_int_o(res, sim, dec2):
 171         out_reg_valid = yield dec2.e.write_reg.ok
 172         if out_reg_valid:
 173             write_reg_idx = yield dec2.e.write_reg.data
 174             res['o'] = sim.gpr(write_reg_idx).value
 175
 176     def get_wr_sim_cr_a(res, sim, dec2):
 177         cridx_ok = yield dec2.e.write_cr.ok
 178         if cridx_ok:
 179             cridx = yield dec2.e.write_cr.data
 180             res['cr_a'] = sim.crl[cridx].get_range().value
 181
 182     def get_wr_sim_xer_ca(res, sim, dec2):
 183         cry_out = yield dec2.e.output_carry
 184         if cry_out:
 185             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 186             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 187             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 188
 189     def get_sim_xer_ov(res, sim, dec2):
 190         oe = yield dec2.e.oe.oe
 191         oe_ok = yield dec2.e.oe.ok
 192         if oe and oe_ok:
 193             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 194             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 195             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 196
 197     def get_sim_xer_so(res, sim, dec2):
 198         oe = yield dec2.e.oe.oe
 199         oe_ok = yield dec2.e.oe.ok
 200         if oe and oe_ok:
 201             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 202
 203     def check_int_o(dut, res, sim_o, msg):
 204         if 'o' in res:
 205             expected = sim_o['o']
 206             alu_out = res['o']
 207             print(f"expected {expected:x}, actual: {alu_out:x}")
 208             dut.assertEqual(expected, alu_out, msg)
 209
 210     def check_cr_a(dut, res, sim_o, msg):
 211         if 'cr_a' in res:
 212             cr_expected = sim_o['cr_a']
 213             cr_actual = res['cr_a']
 214             print ("CR", cr_expected, cr_actual)
 215             dut.assertEqual(cr_expected, cr_actual, msg)
 216
 217     def check_xer_ca(dut, res, sim_o, msg):
 218         if 'xer_ca' in res:
 219             ca_expected = sim_o['xer_ca']
 220             ca_actual = res['xer_ca']
 221             print ("CA", ca_expected, ca_actual)
 222             dut.assertEqual(ca_expected, ca_actual, msg)
 223
 224     def check_xer_ov(dut, res, sim_o, msg):
 225         if 'xer_ov' in res:
 226             ov_expected = sim_o['xer_ov']
 227             ov_actual = res['xer_ov']
 228             print ("OV", ov_expected, ov_actual)
 229             dut.assertEqual(ov_expected, ov_actual, msg)
 230
 231     def check_xer_so(dut, res, sim_o, msg):
 232         if 'xer_so' in res:
 233             so_expected = sim_o['xer_so']
 234             so_actual = res['xer_so']
 235             print ("SO", so_expected, so_actual)
 236             dut.assertEqual(so_expected, so_actual, msg)
 237