src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8 from soc.regfile.regfiles import FastRegs
   9
  10
  11 class TestCase:
  12     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  13                        msr=0,
  14                        do_sim=True):
  15
  16         self.program = program
  17         self.name = name
  18
  19         if regs is None:
  20             regs = [0] * 32
  21         if sprs is None:
  22             sprs = {}
  23         if mem is None:
  24             mem = {}
  25         self.regs = regs
  26         self.sprs = sprs
  27         self.cr = cr
  28         self.mem = mem
  29         self.msr = msr
  30         self.do_sim = do_sim
  31
  32
  33 class ALUHelpers:
  34
  35     def get_sim_fast_reg(res, sim, dec2, reg, name):
  36         spr_sel = fast_reg_to_spr(reg)
  37         spr_data = sim.spr[spr_sel].value
  38         res[name] = spr_data
  39
  40     def get_sim_cia(res, sim, dec2):
  41         res['cia'] = sim.pc.CIA.value
  42
  43     # use this *after* the simulation has run a step (it returns CIA)
  44     def get_sim_nia(res, sim, dec2):
  45         res['nia'] = sim.pc.CIA.value
  46
  47     def get_sim_msr(res, sim, dec2):
  48         res['msr'] = sim.msr.value
  49
  50     def get_sim_slow_spr1(res, sim, dec2):
  51         spr1_en = yield dec2.e.read_spr1.ok
  52         if spr1_en:
  53             spr1_sel = yield dec2.e.read_spr1.data
  54             spr1_data = sim.spr[spr1_sel].value
  55             res['spr1'] = spr1_data
  56
  57     def get_sim_fast_spr1(res, sim, dec2):
  58         fast1_en = yield dec2.e.read_fast1.ok
  59         if fast1_en:
  60             fast1_sel = yield dec2.e.read_fast1.data
  61             spr1_sel = fast_reg_to_spr(fast1_sel)
  62             spr1_data = sim.spr[spr1_sel].value
  63             res['fast1'] = spr1_data
  64
  65     def get_sim_fast_spr2(res, sim, dec2):
  66         fast2_en = yield dec2.e.read_fast2.ok
  67         if fast2_en:
  68             fast2_sel = yield dec2.e.read_fast2.data
  69             spr2_sel = fast_reg_to_spr(fast2_sel)
  70             spr2_data = sim.spr[spr2_sel].value
  71             res['fast2'] = spr2_data
  72
  73     def get_sim_cr_a(res, sim, dec2):
  74         cridx_ok = yield dec2.e.read_cr1.ok
  75         if cridx_ok:
  76             cridx = yield dec2.e.read_cr1.data
  77             res['cr_a'] = sim.crl[cridx].get_range().value
  78
  79     def get_sim_int_ra(res, sim, dec2):
  80         # TODO: immediate RA zero
  81         reg1_ok = yield dec2.e.read_reg1.ok
  82         if reg1_ok:
  83             data1 = yield dec2.e.read_reg1.data
  84             res['ra'] = sim.gpr(data1).value
  85
  86     def get_sim_int_rb(res, sim, dec2):
  87         reg2_ok = yield dec2.e.read_reg2.ok
  88         if reg2_ok:
  89             data = yield dec2.e.read_reg2.data
  90             res['rb'] = sim.gpr(data).value
  91
  92     def get_sim_int_rc(res, sim, dec2):
  93         reg3_ok = yield dec2.e.read_reg3.ok
  94         if reg3_ok:
  95             data = yield dec2.e.read_reg3.data
  96             res['rc'] = sim.gpr(data).value
  97
  98     def get_rd_sim_xer_ca(res, sim, dec2):
  99         cry_in = yield dec2.e.do.input_carry
 100         xer_in = yield dec2.e.xer_in
 101         if xer_in or cry_in == CryIn.CA.value:
 102             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 103             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 104             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 105
 106     def set_int_ra(alu, dec2, inp):
 107         # TODO: immediate RA zero.
 108         if 'ra' in inp:
 109             yield alu.p.data_i.ra.eq(inp['ra'])
 110         else:
 111             yield alu.p.data_i.ra.eq(0)
 112
 113     def set_int_rb(alu, dec2, inp):
 114         yield alu.p.data_i.rb.eq(0)
 115         if 'rb' in inp:
 116             yield alu.p.data_i.rb.eq(inp['rb'])
 117         # If there's an immediate, set the B operand to that
 118         imm_ok = yield dec2.e.do.imm_data.imm_ok
 119         if imm_ok:
 120             data2 = yield dec2.e.do.imm_data.imm
 121             yield alu.p.data_i.rb.eq(data2)
 122
 123     def set_int_rc(alu, dec2, inp):
 124         if 'rc' in inp:
 125             yield alu.p.data_i.rc.eq(inp['rc'])
 126         else:
 127             yield alu.p.data_i.rc.eq(0)
 128
 129     def set_xer_ca(alu, dec2, inp):
 130         if 'xer_ca' in inp:
 131             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 132             print ("extra inputs: CA/32", bin(inp['xer_ca']))
 133
 134     def set_xer_ov(alu, dec2, inp):
 135         if 'xer_ov' in inp:
 136             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 137             print ("extra inputs: OV/32", bin(inp['xer_ov']))
 138
 139     def set_xer_so(alu, dec2, inp):
 140         if 'xer_so' in inp:
 141             so = inp['xer_so']
 142             print ("extra inputs: so", so)
 143             yield alu.p.data_i.xer_so.eq(so)
 144
 145     def set_msr(alu, dec2, inp):
 146         if 'msr' in inp:
 147             yield alu.p.data_i.msr.eq(inp['msr'])
 148
 149     def set_cia(alu, dec2, inp):
 150         if 'cia' in inp:
 151             yield alu.p.data_i.cia.eq(inp['cia'])
 152
 153     def set_slow_spr1(alu, dec2, inp):
 154         if 'spr1' in inp:
 155             yield alu.p.data_i.spr1.eq(inp['spr1'])
 156
 157     def set_slow_spr2(alu, dec2, inp):
 158         if 'spr2' in inp:
 159             yield alu.p.data_i.spr2.eq(inp['spr2'])
 160
 161     def set_fast_spr1(alu, dec2, inp):
 162         if 'fast1' in inp:
 163             yield alu.p.data_i.fast1.eq(inp['fast1'])
 164
 165     def set_fast_spr2(alu, dec2, inp):
 166         if 'fast2' in inp:
 167             yield alu.p.data_i.fast2.eq(inp['fast2'])
 168
 169     def set_cr_a(alu, dec2, inp):
 170         if 'cr_a' in inp:
 171             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 172
 173     def set_cr_b(alu, dec2, inp):
 174         if 'cr_b' in inp:
 175             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 176
 177     def set_cr_c(alu, dec2, inp):
 178         if 'cr_c' in inp:
 179             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 180
 181     def set_full_cr(alu, dec2, inp):
 182         if 'full_cr' in inp:
 183             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 184         else:
 185             yield alu.p.data_i.full_cr.eq(0)
 186
 187     def get_slow_spr1(res, alu, dec2):
 188         spr1_valid = yield alu.n.data_o.spr1.ok
 189         if spr1_valid:
 190             res['spr1'] = yield alu.n.data_o.spr1.data
 191
 192     def get_slow_spr2(res, alu, dec2):
 193         spr2_valid = yield alu.n.data_o.spr2.ok
 194         if spr2_valid:
 195             res['spr2'] = yield alu.n.data_o.spr2.data
 196
 197     def get_fast_spr1(res, alu, dec2):
 198         spr1_valid = yield alu.n.data_o.fast1.ok
 199         if spr1_valid:
 200             res['fast1'] = yield alu.n.data_o.fast1.data
 201
 202     def get_fast_spr2(res, alu, dec2):
 203         spr2_valid = yield alu.n.data_o.fast2.ok
 204         if spr2_valid:
 205             res['fast2'] = yield alu.n.data_o.fast2.data
 206
 207     def get_cia(res, alu, dec2):
 208         res['cia'] = yield alu.p.data_i.cia
 209
 210     def get_nia(res, alu, dec2):
 211         nia_valid = yield alu.n.data_o.nia.ok
 212         if nia_valid:
 213             res['nia'] = yield alu.n.data_o.nia.data
 214
 215     def get_msr(res, alu, dec2):
 216         msr_valid = yield alu.n.data_o.msr.ok
 217         if msr_valid:
 218             res['msr'] = yield alu.n.data_o.msr.data
 219
 220     def get_int_o1(res, alu, dec2):
 221         out_reg_valid = yield dec2.e.write_ea.ok
 222         if out_reg_valid:
 223             res['o1'] = yield alu.n.data_o.o1.data
 224
 225     def get_int_o(res, alu, dec2):
 226         out_reg_valid = yield dec2.e.write_reg.ok
 227         if out_reg_valid:
 228             res['o'] = yield alu.n.data_o.o.data
 229
 230     def get_cr_a(res, alu, dec2):
 231         cridx_ok = yield dec2.e.write_cr.ok
 232         if cridx_ok:
 233             res['cr_a'] = yield alu.n.data_o.cr0.data
 234
 235     def get_xer_so(res, alu, dec2):
 236         oe = yield dec2.e.do.oe.oe
 237         oe_ok = yield dec2.e.do.oe.ok
 238         xer_out = yield dec2.e.xer_out
 239         if not (yield alu.n.data_o.xer_so.ok):
 240             return
 241         if xer_out or (oe and oe_ok):
 242             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 243
 244     def get_xer_ov(res, alu, dec2):
 245         oe = yield dec2.e.do.oe.oe
 246         oe_ok = yield dec2.e.do.oe.ok
 247         xer_out = yield dec2.e.xer_out
 248         if not (yield alu.n.data_o.xer_ov.ok):
 249             return
 250         if xer_out or (oe and oe_ok):
 251             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 252
 253     def get_xer_ca(res, alu, dec2):
 254         cry_out = yield dec2.e.do.output_carry
 255         xer_out = yield dec2.e.xer_out
 256         if not (yield alu.n.data_o.xer_ca.ok):
 257             return
 258         if xer_out or (cry_out):
 259             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 260
 261     def get_sim_int_o(res, sim, dec2):
 262         out_reg_valid = yield dec2.e.write_reg.ok
 263         if out_reg_valid:
 264             write_reg_idx = yield dec2.e.write_reg.data
 265             res['o'] = sim.gpr(write_reg_idx).value
 266
 267     def get_sim_int_o1(res, sim, dec2):
 268         out_reg_valid = yield dec2.e.write_ea.ok
 269         if out_reg_valid:
 270             write_reg_idx = yield dec2.e.write_ea.data
 271             res['o1'] = sim.gpr(write_reg_idx).value
 272
 273     def get_wr_sim_cr_a(res, sim, dec2):
 274         cridx_ok = yield dec2.e.write_cr.ok
 275         if cridx_ok:
 276             cridx = yield dec2.e.write_cr.data
 277             res['cr_a'] = sim.crl[cridx].get_range().value
 278
 279     def get_wr_fast_spr2(res, sim, dec2):
 280         ok = yield dec2.e.write_fast2.ok
 281         if ok:
 282             spr_num = yield dec2.e.write_fast2.data
 283             spr_num = fast_reg_to_spr(spr_num)
 284             spr_name = spr_dict[spr_num].SPR
 285             res['fast2'] = sim.spr[spr_name].value
 286
 287     def get_wr_fast_spr1(res, sim, dec2):
 288         ok = yield dec2.e.write_fast1.ok
 289         if ok:
 290             spr_num = yield dec2.e.write_fast1.data
 291             spr_num = fast_reg_to_spr(spr_num)
 292             spr_name = spr_dict[spr_num].SPR
 293             res['fast1'] = sim.spr[spr_name].value
 294
 295     def get_wr_slow_spr1(res, sim, dec2):
 296         ok = yield dec2.e.write_spr.ok
 297         if ok:
 298             spr_num = yield dec2.e.write_spr.data
 299             spr_name = spr_dict[spr_num].SPR
 300             res['spr1'] = sim.spr[spr_name].value
 301
 302     def get_wr_sim_xer_ca(res, sim, dec2):
 303         #if not (yield alu.n.data_o.xer_ca.ok):
 304         #    return
 305         cry_out = yield dec2.e.do.output_carry
 306         xer_out = yield dec2.e.xer_out
 307         if cry_out or xer_out:
 308             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 309             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 310             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 311
 312     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 313         oe = yield dec2.e.do.oe.oe
 314         oe_ok = yield dec2.e.do.oe.ok
 315         xer_out = yield dec2.e.xer_out
 316         print ("get_wr_sim_xer_ov", xer_out)
 317         if not (yield alu.n.data_o.xer_ov.ok):
 318             return
 319         if xer_out or (oe and oe_ok):
 320             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 321             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 322             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 323
 324     def get_wr_sim_xer_so(res, sim, alu, dec2):
 325         oe = yield dec2.e.do.oe.oe
 326         oe_ok = yield dec2.e.do.oe.ok
 327         xer_out = yield dec2.e.xer_out
 328         if not (yield alu.n.data_o.xer_so.ok):
 329             return
 330         if xer_out or (oe and oe_ok):
 331             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 332
 333     def get_sim_xer_ov(res, sim, dec2):
 334         oe = yield dec2.e.do.oe.oe
 335         oe_ok = yield dec2.e.do.oe.ok
 336         xer_in = yield dec2.e.xer_in
 337         print ("get_sim_xer_ov", xer_in)
 338         if xer_in or (oe and oe_ok):
 339             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 340             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 341             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 342
 343     def get_sim_xer_so(res, sim, dec2):
 344         oe = yield dec2.e.do.oe.oe
 345         oe_ok = yield dec2.e.do.oe.ok
 346         xer_in = yield dec2.e.xer_in
 347         if xer_in or (oe and oe_ok):
 348             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 349
 350     def check_slow_spr1(dut, res, sim_o, msg):
 351         if 'spr1' in res:
 352             expected = sim_o['spr1']
 353             alu_out = res['spr1']
 354             print(f"expected {expected:x}, actual: {alu_out:x}")
 355             dut.assertEqual(expected, alu_out, msg)
 356
 357     def check_fast_spr1(dut, res, sim_o, msg):
 358         if 'fast1' in res:
 359             expected = sim_o['fast1']
 360             alu_out = res['fast1']
 361             print(f"expected {expected:x}, actual: {alu_out:x}")
 362             dut.assertEqual(expected, alu_out, msg)
 363
 364     def check_fast_spr2(dut, res, sim_o, msg):
 365         if 'fast2' in res:
 366             expected = sim_o['fast2']
 367             alu_out = res['fast2']
 368             print(f"expected {expected:x}, actual: {alu_out:x}")
 369             dut.assertEqual(expected, alu_out, msg)
 370
 371     def check_int_o1(dut, res, sim_o, msg):
 372         if 'o1' in res:
 373             expected = sim_o['o1']
 374             alu_out = res['o1']
 375             print(f"expected {expected:x}, actual: {alu_out:x}")
 376             dut.assertEqual(expected, alu_out, msg)
 377
 378     def check_int_o(dut, res, sim_o, msg):
 379         if 'o' in res:
 380             expected = sim_o['o']
 381             alu_out = res['o']
 382             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 383             dut.assertEqual(expected, alu_out, msg)
 384
 385     def check_msr(dut, res, sim_o, msg):
 386         if 'msr' in res:
 387             expected = sim_o['msr']
 388             alu_out = res['msr']
 389             print(f"expected {expected:x}, actual: {alu_out:x}")
 390             dut.assertEqual(expected, alu_out, msg)
 391
 392     def check_nia(dut, res, sim_o, msg):
 393         if 'nia' in res:
 394             expected = sim_o['nia']
 395             alu_out = res['nia']
 396             print(f"expected {expected:x}, actual: {alu_out:x}")
 397             dut.assertEqual(expected, alu_out, msg)
 398
 399     def check_cr_a(dut, res, sim_o, msg):
 400         if 'cr_a' in res:
 401             cr_expected = sim_o['cr_a']
 402             cr_actual = res['cr_a']
 403             print ("CR", cr_expected, cr_actual)
 404             dut.assertEqual(cr_expected, cr_actual, msg)
 405
 406     def check_xer_ca(dut, res, sim_o, msg):
 407         if 'xer_ca' in res:
 408             ca_expected = sim_o['xer_ca']
 409             ca_actual = res['xer_ca']
 410             print ("CA", ca_expected, ca_actual)
 411             dut.assertEqual(ca_expected, ca_actual, msg)
 412
 413     def check_xer_ov(dut, res, sim_o, msg):
 414         if 'xer_ov' in res:
 415             ov_expected = sim_o['xer_ov']
 416             ov_actual = res['xer_ov']
 417             print ("OV", ov_expected, ov_actual)
 418             dut.assertEqual(ov_expected, ov_actual, msg)
 419
 420     def check_xer_so(dut, res, sim_o, msg):
 421         if 'xer_so' in res:
 422             so_expected = sim_o['xer_so']
 423             so_actual = res['xer_so']
 424             print ("SO", so_expected, so_actual)
 425             dut.assertEqual(so_expected, so_actual, msg)
 426