3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
6 from soc
.decoder
.power_enums
import XER_bits
, CryIn
, spr_dict
7 from soc
.regfile
.util
import fast_reg_to_spr
# HACK!
8 from soc
.regfile
.regfiles
import FastRegs
12 def __init__(self
, program
, name
, regs
=None, sprs
=None, cr
=0, mem
=None,
15 extra_break_addr
=None):
17 self
.program
= program
32 self
.extra_break_addr
= extra_break_addr
37 def get_sim_fast_reg(res
, sim
, dec2
, reg
, name
):
38 spr_sel
= fast_reg_to_spr(reg
)
39 spr_data
= sim
.spr
[spr_sel
].value
42 def get_sim_cia(res
, sim
, dec2
):
43 res
['cia'] = sim
.pc
.CIA
.value
45 # use this *after* the simulation has run a step (it returns CIA)
46 def get_sim_nia(res
, sim
, dec2
):
47 res
['nia'] = sim
.pc
.CIA
.value
49 def get_sim_msr(res
, sim
, dec2
):
50 res
['msr'] = sim
.msr
.value
52 def get_sim_slow_spr1(res
, sim
, dec2
):
53 spr1_en
= yield dec2
.e
.read_spr1
.ok
55 spr1_sel
= yield dec2
.e
.read_spr1
.data
56 spr1_data
= sim
.spr
[spr1_sel
].value
57 res
['spr1'] = spr1_data
59 def get_sim_fast_spr1(res
, sim
, dec2
):
60 fast1_en
= yield dec2
.e
.read_fast1
.ok
62 fast1_sel
= yield dec2
.e
.read_fast1
.data
63 spr1_sel
= fast_reg_to_spr(fast1_sel
)
64 spr1_data
= sim
.spr
[spr1_sel
].value
65 res
['fast1'] = spr1_data
67 def get_sim_fast_spr2(res
, sim
, dec2
):
68 fast2_en
= yield dec2
.e
.read_fast2
.ok
70 fast2_sel
= yield dec2
.e
.read_fast2
.data
71 spr2_sel
= fast_reg_to_spr(fast2_sel
)
72 spr2_data
= sim
.spr
[spr2_sel
].value
73 res
['fast2'] = spr2_data
75 def get_sim_cr_a(res
, sim
, dec2
):
76 cridx_ok
= yield dec2
.e
.read_cr1
.ok
78 cridx
= yield dec2
.e
.read_cr1
.data
79 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
81 def get_sim_int_ra(res
, sim
, dec2
):
82 # TODO: immediate RA zero
83 reg1_ok
= yield dec2
.e
.read_reg1
.ok
85 data1
= yield dec2
.e
.read_reg1
.data
86 res
['ra'] = sim
.gpr(data1
).value
88 def get_sim_int_rb(res
, sim
, dec2
):
89 reg2_ok
= yield dec2
.e
.read_reg2
.ok
91 data
= yield dec2
.e
.read_reg2
.data
92 res
['rb'] = sim
.gpr(data
).value
94 def get_sim_int_rc(res
, sim
, dec2
):
95 reg3_ok
= yield dec2
.e
.read_reg3
.ok
97 data
= yield dec2
.e
.read_reg3
.data
98 res
['rc'] = sim
.gpr(data
).value
100 def get_rd_sim_xer_ca(res
, sim
, dec2
):
101 cry_in
= yield dec2
.e
.do
.input_carry
102 xer_in
= yield dec2
.e
.xer_in
103 if xer_in
or cry_in
== CryIn
.CA
.value
:
104 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
105 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
106 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
108 def set_int_ra(alu
, dec2
, inp
):
109 # TODO: immediate RA zero.
111 yield alu
.p
.data_i
.ra
.eq(inp
['ra'])
113 yield alu
.p
.data_i
.ra
.eq(0)
115 def set_int_rb(alu
, dec2
, inp
):
116 yield alu
.p
.data_i
.rb
.eq(0)
118 yield alu
.p
.data_i
.rb
.eq(inp
['rb'])
119 # If there's an immediate, set the B operand to that
120 imm_ok
= yield dec2
.e
.do
.imm_data
.imm_ok
122 data2
= yield dec2
.e
.do
.imm_data
.imm
123 yield alu
.p
.data_i
.rb
.eq(data2
)
125 def set_int_rc(alu
, dec2
, inp
):
127 yield alu
.p
.data_i
.rc
.eq(inp
['rc'])
129 yield alu
.p
.data_i
.rc
.eq(0)
131 def set_xer_ca(alu
, dec2
, inp
):
133 yield alu
.p
.data_i
.xer_ca
.eq(inp
['xer_ca'])
134 print ("extra inputs: CA/32", bin(inp
['xer_ca']))
136 def set_xer_ov(alu
, dec2
, inp
):
138 yield alu
.p
.data_i
.xer_ov
.eq(inp
['xer_ov'])
139 print ("extra inputs: OV/32", bin(inp
['xer_ov']))
141 def set_xer_so(alu
, dec2
, inp
):
144 print ("extra inputs: so", so
)
145 yield alu
.p
.data_i
.xer_so
.eq(so
)
147 def set_msr(alu
, dec2
, inp
):
149 yield alu
.p
.data_i
.msr
.eq(inp
['msr'])
151 def set_cia(alu
, dec2
, inp
):
153 yield alu
.p
.data_i
.cia
.eq(inp
['cia'])
155 def set_slow_spr1(alu
, dec2
, inp
):
157 yield alu
.p
.data_i
.spr1
.eq(inp
['spr1'])
159 def set_slow_spr2(alu
, dec2
, inp
):
161 yield alu
.p
.data_i
.spr2
.eq(inp
['spr2'])
163 def set_fast_spr1(alu
, dec2
, inp
):
165 yield alu
.p
.data_i
.fast1
.eq(inp
['fast1'])
167 def set_fast_spr2(alu
, dec2
, inp
):
169 yield alu
.p
.data_i
.fast2
.eq(inp
['fast2'])
171 def set_cr_a(alu
, dec2
, inp
):
173 yield alu
.p
.data_i
.cr_a
.eq(inp
['cr_a'])
175 def set_cr_b(alu
, dec2
, inp
):
177 yield alu
.p
.data_i
.cr_b
.eq(inp
['cr_b'])
179 def set_cr_c(alu
, dec2
, inp
):
181 yield alu
.p
.data_i
.cr_c
.eq(inp
['cr_c'])
183 def set_full_cr(alu
, dec2
, inp
):
185 yield alu
.p
.data_i
.full_cr
.eq(inp
['full_cr'])
187 yield alu
.p
.data_i
.full_cr
.eq(0)
189 def get_slow_spr1(res
, alu
, dec2
):
190 spr1_valid
= yield alu
.n
.data_o
.spr1
.ok
192 res
['spr1'] = yield alu
.n
.data_o
.spr1
.data
194 def get_slow_spr2(res
, alu
, dec2
):
195 spr2_valid
= yield alu
.n
.data_o
.spr2
.ok
197 res
['spr2'] = yield alu
.n
.data_o
.spr2
.data
199 def get_fast_spr1(res
, alu
, dec2
):
200 spr1_valid
= yield alu
.n
.data_o
.fast1
.ok
202 res
['fast1'] = yield alu
.n
.data_o
.fast1
.data
204 def get_fast_spr2(res
, alu
, dec2
):
205 spr2_valid
= yield alu
.n
.data_o
.fast2
.ok
207 res
['fast2'] = yield alu
.n
.data_o
.fast2
.data
209 def get_cia(res
, alu
, dec2
):
210 res
['cia'] = yield alu
.p
.data_i
.cia
212 def get_nia(res
, alu
, dec2
):
213 nia_valid
= yield alu
.n
.data_o
.nia
.ok
215 res
['nia'] = yield alu
.n
.data_o
.nia
.data
217 def get_msr(res
, alu
, dec2
):
218 msr_valid
= yield alu
.n
.data_o
.msr
.ok
220 res
['msr'] = yield alu
.n
.data_o
.msr
.data
222 def get_int_o1(res
, alu
, dec2
):
223 out_reg_valid
= yield dec2
.e
.write_ea
.ok
225 res
['o1'] = yield alu
.n
.data_o
.o1
.data
227 def get_int_o(res
, alu
, dec2
):
228 out_reg_valid
= yield dec2
.e
.write_reg
.ok
230 res
['o'] = yield alu
.n
.data_o
.o
.data
232 def get_cr_a(res
, alu
, dec2
):
233 cridx_ok
= yield dec2
.e
.write_cr
.ok
235 res
['cr_a'] = yield alu
.n
.data_o
.cr0
.data
237 def get_xer_so(res
, alu
, dec2
):
238 oe
= yield dec2
.e
.do
.oe
.oe
239 oe_ok
= yield dec2
.e
.do
.oe
.ok
240 xer_out
= yield dec2
.e
.xer_out
241 if not (yield alu
.n
.data_o
.xer_so
.ok
):
243 if xer_out
or (oe
and oe_ok
):
244 res
['xer_so'] = yield alu
.n
.data_o
.xer_so
.data
[0]
246 def get_xer_ov(res
, alu
, dec2
):
247 oe
= yield dec2
.e
.do
.oe
.oe
248 oe_ok
= yield dec2
.e
.do
.oe
.ok
249 xer_out
= yield dec2
.e
.xer_out
250 if not (yield alu
.n
.data_o
.xer_ov
.ok
):
252 if xer_out
or (oe
and oe_ok
):
253 res
['xer_ov'] = yield alu
.n
.data_o
.xer_ov
.data
255 def get_xer_ca(res
, alu
, dec2
):
256 cry_out
= yield dec2
.e
.do
.output_carry
257 xer_out
= yield dec2
.e
.xer_out
258 if not (yield alu
.n
.data_o
.xer_ca
.ok
):
260 if xer_out
or (cry_out
):
261 res
['xer_ca'] = yield alu
.n
.data_o
.xer_ca
.data
263 def get_sim_int_o(res
, sim
, dec2
):
264 out_reg_valid
= yield dec2
.e
.write_reg
.ok
266 write_reg_idx
= yield dec2
.e
.write_reg
.data
267 res
['o'] = sim
.gpr(write_reg_idx
).value
269 def get_sim_int_o1(res
, sim
, dec2
):
270 out_reg_valid
= yield dec2
.e
.write_ea
.ok
272 write_reg_idx
= yield dec2
.e
.write_ea
.data
273 res
['o1'] = sim
.gpr(write_reg_idx
).value
275 def get_wr_sim_cr_a(res
, sim
, dec2
):
276 cridx_ok
= yield dec2
.e
.write_cr
.ok
278 cridx
= yield dec2
.e
.write_cr
.data
279 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
281 def get_wr_fast_spr2(res
, sim
, dec2
):
282 ok
= yield dec2
.e
.write_fast2
.ok
284 spr_num
= yield dec2
.e
.write_fast2
.data
285 spr_num
= fast_reg_to_spr(spr_num
)
286 spr_name
= spr_dict
[spr_num
].SPR
287 res
['fast2'] = sim
.spr
[spr_name
].value
289 def get_wr_fast_spr1(res
, sim
, dec2
):
290 ok
= yield dec2
.e
.write_fast1
.ok
292 spr_num
= yield dec2
.e
.write_fast1
.data
293 spr_num
= fast_reg_to_spr(spr_num
)
294 spr_name
= spr_dict
[spr_num
].SPR
295 res
['fast1'] = sim
.spr
[spr_name
].value
297 def get_wr_slow_spr1(res
, sim
, dec2
):
298 ok
= yield dec2
.e
.write_spr
.ok
300 spr_num
= yield dec2
.e
.write_spr
.data
301 spr_name
= spr_dict
[spr_num
].SPR
302 res
['spr1'] = sim
.spr
[spr_name
].value
304 def get_wr_sim_xer_ca(res
, sim
, dec2
):
305 #if not (yield alu.n.data_o.xer_ca.ok):
307 cry_out
= yield dec2
.e
.do
.output_carry
308 xer_out
= yield dec2
.e
.xer_out
309 if cry_out
or xer_out
:
310 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
311 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
312 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
314 def get_wr_sim_xer_ov(res
, sim
, alu
, dec2
):
315 oe
= yield dec2
.e
.do
.oe
.oe
316 oe_ok
= yield dec2
.e
.do
.oe
.ok
317 xer_out
= yield dec2
.e
.xer_out
318 print ("get_wr_sim_xer_ov", xer_out
)
319 if not (yield alu
.n
.data_o
.xer_ov
.ok
):
321 if xer_out
or (oe
and oe_ok
):
322 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
323 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
324 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
326 def get_wr_sim_xer_so(res
, sim
, alu
, dec2
):
327 oe
= yield dec2
.e
.do
.oe
.oe
328 oe_ok
= yield dec2
.e
.do
.oe
.ok
329 xer_out
= yield dec2
.e
.xer_out
330 if not (yield alu
.n
.data_o
.xer_so
.ok
):
332 if xer_out
or (oe
and oe_ok
):
333 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
335 def get_sim_xer_ov(res
, sim
, dec2
):
336 oe
= yield dec2
.e
.do
.oe
.oe
337 oe_ok
= yield dec2
.e
.do
.oe
.ok
338 xer_in
= yield dec2
.e
.xer_in
339 print ("get_sim_xer_ov", xer_in
)
340 if xer_in
or (oe
and oe_ok
):
341 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
342 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
343 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
345 def get_sim_xer_so(res
, sim
, dec2
):
346 oe
= yield dec2
.e
.do
.oe
.oe
347 oe_ok
= yield dec2
.e
.do
.oe
.ok
348 xer_in
= yield dec2
.e
.xer_in
349 if xer_in
or (oe
and oe_ok
):
350 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
352 def check_slow_spr1(dut
, res
, sim_o
, msg
):
354 expected
= sim_o
['spr1']
355 alu_out
= res
['spr1']
356 print(f
"expected {expected:x}, actual: {alu_out:x}")
357 dut
.assertEqual(expected
, alu_out
, msg
)
359 def check_fast_spr1(dut
, res
, sim_o
, msg
):
361 expected
= sim_o
['fast1']
362 alu_out
= res
['fast1']
363 print(f
"expected {expected:x}, actual: {alu_out:x}")
364 dut
.assertEqual(expected
, alu_out
, msg
)
366 def check_fast_spr2(dut
, res
, sim_o
, msg
):
368 expected
= sim_o
['fast2']
369 alu_out
= res
['fast2']
370 print(f
"expected {expected:x}, actual: {alu_out:x}")
371 dut
.assertEqual(expected
, alu_out
, msg
)
373 def check_int_o1(dut
, res
, sim_o
, msg
):
375 expected
= sim_o
['o1']
377 print(f
"expected {expected:x}, actual: {alu_out:x}")
378 dut
.assertEqual(expected
, alu_out
, msg
)
380 def check_int_o(dut
, res
, sim_o
, msg
):
382 expected
= sim_o
['o']
384 print(f
"expected int sim {expected:x}, actual: {alu_out:x}")
385 dut
.assertEqual(expected
, alu_out
, msg
)
387 def check_msr(dut
, res
, sim_o
, msg
):
389 expected
= sim_o
['msr']
391 print(f
"expected {expected:x}, actual: {alu_out:x}")
392 dut
.assertEqual(expected
, alu_out
, msg
)
394 def check_nia(dut
, res
, sim_o
, msg
):
396 expected
= sim_o
['nia']
398 print(f
"expected {expected:x}, actual: {alu_out:x}")
399 dut
.assertEqual(expected
, alu_out
, msg
)
401 def check_cr_a(dut
, res
, sim_o
, msg
):
403 cr_expected
= sim_o
['cr_a']
404 cr_actual
= res
['cr_a']
405 print ("CR", cr_expected
, cr_actual
)
406 dut
.assertEqual(cr_expected
, cr_actual
, msg
)
408 def check_xer_ca(dut
, res
, sim_o
, msg
):
410 ca_expected
= sim_o
['xer_ca']
411 ca_actual
= res
['xer_ca']
412 print ("CA", ca_expected
, ca_actual
)
413 dut
.assertEqual(ca_expected
, ca_actual
, msg
)
415 def check_xer_ov(dut
, res
, sim_o
, msg
):
417 ov_expected
= sim_o
['xer_ov']
418 ov_actual
= res
['xer_ov']
419 print ("OV", ov_expected
, ov_actual
)
420 dut
.assertEqual(ov_expected
, ov_actual
, msg
)
422 def check_xer_so(dut
, res
, sim_o
, msg
):
424 so_expected
= sim_o
['xer_so']
425 so_actual
= res
['xer_so']
426 print ("SO", so_expected
, so_actual
)
427 dut
.assertEqual(so_expected
, so_actual
, msg
)