src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8 from soc.regfile.regfiles import FastRegs
   9
  10
  11 class TestCase:
  12     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  13                        msr=0):
  14
  15         self.program = program
  16         self.name = name
  17
  18         if regs is None:
  19             regs = [0] * 32
  20         if sprs is None:
  21             sprs = {}
  22         if mem is None:
  23             mem = {}
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.cr = cr
  27         self.mem = mem
  28         self.msr = msr
  29
  30 class ALUHelpers:
  31
  32     def get_sim_fast_reg(res, sim, dec2, reg, name):
  33         spr_sel = fast_reg_to_spr(reg)
  34         spr_data = sim.spr[spr_sel].value
  35         res[name] = spr_data
  36
  37     def get_sim_cia(res, sim, dec2):
  38         res['cia'] = sim.pc.CIA.value
  39
  40     def get_sim_msr(res, sim, dec2):
  41         res['msr'] = sim.msr.value
  42
  43     def get_sim_fast_spr1(res, sim, dec2):
  44         fast1_en = yield dec2.e.read_fast1.ok
  45         if fast1_en:
  46             fast1_sel = yield dec2.e.read_fast1.data
  47             spr1_sel = fast_reg_to_spr(fast1_sel)
  48             spr1_data = sim.spr[spr1_sel].value
  49             res['fast1'] = spr1_data
  50
  51     def get_sim_fast_spr2(res, sim, dec2):
  52         fast2_en = yield dec2.e.read_fast2.ok
  53         if fast2_en:
  54             fast2_sel = yield dec2.e.read_fast2.data
  55             spr2_sel = fast_reg_to_spr(fast2_sel)
  56             spr2_data = sim.spr[spr2_sel].value
  57             res['fast2'] = spr2_data
  58
  59     def get_sim_cr_a(res, sim, dec2):
  60         cridx_ok = yield dec2.e.read_cr1.ok
  61         if cridx_ok:
  62             cridx = yield dec2.e.read_cr1.data
  63             res['cr_a'] = sim.crl[cridx].get_range().value
  64
  65     def get_sim_int_ra(res, sim, dec2):
  66         # TODO: immediate RA zero
  67         reg1_ok = yield dec2.e.read_reg1.ok
  68         if reg1_ok:
  69             data1 = yield dec2.e.read_reg1.data
  70             res['ra'] = sim.gpr(data1).value
  71
  72     def get_sim_int_rb(res, sim, dec2):
  73         reg2_ok = yield dec2.e.read_reg2.ok
  74         if reg2_ok:
  75             data = yield dec2.e.read_reg2.data
  76             res['rb'] = sim.gpr(data).value
  77
  78     def get_sim_int_rc(res, sim, dec2):
  79         reg3_ok = yield dec2.e.read_reg3.ok
  80         if reg3_ok:
  81             data = yield dec2.e.read_reg3.data
  82             res['rc'] = sim.gpr(data).value
  83
  84     def get_rd_sim_xer_ca(res, sim, dec2):
  85         cry_in = yield dec2.e.input_carry
  86         if cry_in == CryIn.CA.value:
  87             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  88             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  89             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
  90
  91     def set_int_ra(alu, dec2, inp):
  92         # TODO: immediate RA zero.
  93         if 'ra' in inp:
  94             yield alu.p.data_i.ra.eq(inp['ra'])
  95         else:
  96             yield alu.p.data_i.ra.eq(0)
  97
  98     def set_int_rb(alu, dec2, inp):
  99         yield alu.p.data_i.rb.eq(0)
 100         if 'rb' in inp:
 101             yield alu.p.data_i.rb.eq(inp['rb'])
 102         # If there's an immediate, set the B operand to that
 103         imm_ok = yield dec2.e.imm_data.imm_ok
 104         if imm_ok:
 105             data2 = yield dec2.e.imm_data.imm
 106             yield alu.p.data_i.rb.eq(data2)
 107
 108     def set_int_rc(alu, dec2, inp):
 109         if 'rc' in inp:
 110             yield alu.p.data_i.rc.eq(inp['rc'])
 111         else:
 112             yield alu.p.data_i.rc.eq(0)
 113
 114     def set_xer_ca(alu, dec2, inp):
 115         if 'xer_ca' in inp:
 116             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 117             print ("extra inputs: CA/32", bin(inp['xer_ca']))
 118
 119     def set_xer_ov(alu, dec2, inp):
 120         if 'xer_ov' in inp:
 121             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 122             print ("extra inputs: OV/32", bin(inp['xer_ov']))
 123
 124     def set_xer_so(alu, dec2, inp):
 125         if 'xer_so' in inp:
 126             so = inp['xer_so']
 127             print ("extra inputs: so", so)
 128             yield alu.p.data_i.xer_so.eq(so)
 129
 130     def set_msr(alu, dec2, inp):
 131         if 'msr' in inp:
 132             yield alu.p.data_i.msr.eq(inp['msr'])
 133
 134     def set_cia(alu, dec2, inp):
 135         if 'cia' in inp:
 136             yield alu.p.data_i.cia.eq(inp['cia'])
 137
 138     def set_slow_spr1(alu, dec2, inp):
 139         if 'spr1' in inp:
 140             yield alu.p.data_i.spr1.eq(inp['spr1'])
 141
 142     def set_slow_spr2(alu, dec2, inp):
 143         if 'spr2' in inp:
 144             yield alu.p.data_i.spr2.eq(inp['spr2'])
 145
 146     def set_fast_spr1(alu, dec2, inp):
 147         if 'fast1' in inp:
 148             yield alu.p.data_i.fast1.eq(inp['fast1'])
 149
 150     def set_fast_spr2(alu, dec2, inp):
 151         if 'fast2' in inp:
 152             yield alu.p.data_i.fast2.eq(inp['fast2'])
 153
 154     def set_cr_a(alu, dec2, inp):
 155         if 'cr_a' in inp:
 156             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 157
 158     def set_cr_b(alu, dec2, inp):
 159         if 'cr_b' in inp:
 160             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 161
 162     def set_cr_c(alu, dec2, inp):
 163         if 'cr_c' in inp:
 164             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 165
 166     def set_full_cr(alu, dec2, inp):
 167         if 'full_cr' in inp:
 168             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 169         else:
 170             yield alu.p.data_i.full_cr.eq(0)
 171
 172     def get_slow_spr1(res, alu, dec2):
 173         spr1_valid = yield alu.n.data_o.spr1.ok
 174         if spr1_valid:
 175             res['spr1'] = yield alu.n.data_o.spr1.data
 176
 177     def get_slow_spr2(res, alu, dec2):
 178         spr2_valid = yield alu.n.data_o.spr2.ok
 179         if spr2_valid:
 180             res['spr2'] = yield alu.n.data_o.spr2.data
 181
 182     def get_fast_spr1(res, alu, dec2):
 183         spr1_valid = yield alu.n.data_o.fast1.ok
 184         if spr1_valid:
 185             res['fast1'] = yield alu.n.data_o.fast1.data
 186
 187     def get_fast_spr2(res, alu, dec2):
 188         spr2_valid = yield alu.n.data_o.fast2.ok
 189         if spr2_valid:
 190             res['fast2'] = yield alu.n.data_o.fast2.data
 191
 192     def get_cia(res, alu, dec2):
 193         res['cia'] = yield alu.p.data_i.cia
 194
 195     def get_nia(res, alu, dec2):
 196         nia_valid = yield alu.n.data_o.nia.ok
 197         if nia_valid:
 198             res['nia'] = yield alu.n.data_o.nia.data
 199
 200     def get_msr(res, alu, dec2):
 201         msr_valid = yield alu.n.data_o.msr.ok
 202         if msr_valid:
 203             res['msr'] = yield alu.n.data_o.msr.data
 204
 205     def get_int_o1(res, alu, dec2):
 206         out_reg_valid = yield dec2.e.write_ea.ok
 207         if out_reg_valid:
 208             res['o1'] = yield alu.n.data_o.o1.data
 209
 210     def get_int_o(res, alu, dec2):
 211         out_reg_valid = yield dec2.e.write_reg.ok
 212         if out_reg_valid:
 213             res['o'] = yield alu.n.data_o.o.data
 214
 215     def get_cr_a(res, alu, dec2):
 216         cridx_ok = yield dec2.e.write_cr.ok
 217         if cridx_ok:
 218             res['cr_a'] = yield alu.n.data_o.cr0.data
 219
 220     def get_xer_so(res, alu, dec2):
 221         oe = yield dec2.e.oe.oe
 222         oe_ok = yield dec2.e.oe.ok
 223         if oe and oe_ok:
 224             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 225
 226     def get_xer_ov(res, alu, dec2):
 227         oe = yield dec2.e.oe.oe
 228         oe_ok = yield dec2.e.oe.ok
 229         if oe and oe_ok:
 230             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 231
 232     def get_xer_ca(res, alu, dec2):
 233         cry_out = yield dec2.e.output_carry
 234         if cry_out:
 235             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 236
 237     def get_sim_int_o(res, sim, dec2):
 238         out_reg_valid = yield dec2.e.write_reg.ok
 239         if out_reg_valid:
 240             write_reg_idx = yield dec2.e.write_reg.data
 241             res['o'] = sim.gpr(write_reg_idx).value
 242
 243     def get_sim_int_o1(res, sim, dec2):
 244         out_reg_valid = yield dec2.e.write_ea.ok
 245         if out_reg_valid:
 246             write_reg_idx = yield dec2.e.write_ea.data
 247             res['o1'] = sim.gpr(write_reg_idx).value
 248
 249     def get_wr_sim_cr_a(res, sim, dec2):
 250         cridx_ok = yield dec2.e.write_cr.ok
 251         if cridx_ok:
 252             cridx = yield dec2.e.write_cr.data
 253             res['cr_a'] = sim.crl[cridx].get_range().value
 254
 255     def get_wr_fast_spr2(res, sim, dec2):
 256         ok = yield dec2.e.write_fast2.ok
 257         if ok:
 258             spr_num = yield dec2.e.write_fast2.data
 259             spr_num = fast_reg_to_spr(spr_num)
 260             spr_name = spr_dict[spr_num]
 261             res['fast2'] = sim.spr[spr_name]
 262
 263     def get_wr_fast_spr1(res, sim, dec2):
 264         ok = yield dec2.e.write_fast1.ok
 265         if ok:
 266             spr_num = yield dec2.e.write_fast1.data
 267             spr_num = fast_reg_to_spr(spr_num)
 268             spr_name = spr_dict[spr_num]
 269             res['fast1'] = sim.spr[spr_name]
 270
 271     def get_wr_sim_xer_ca(res, sim, dec2):
 272         cry_out = yield dec2.e.output_carry
 273         if cry_out:
 274             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 275             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 276             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 277
 278     def get_sim_xer_ov(res, sim, dec2):
 279         oe = yield dec2.e.oe.oe
 280         oe_ok = yield dec2.e.oe.ok
 281         if oe and oe_ok:
 282             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 283             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 284             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 285
 286     def get_sim_xer_so(res, sim, dec2):
 287         oe = yield dec2.e.oe.oe
 288         oe_ok = yield dec2.e.oe.ok
 289         if oe and oe_ok:
 290             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 291
 292     def check_fast_spr1(dut, res, sim_o, msg):
 293         if 'fast1' in res:
 294             expected = sim_o['fast1']
 295             alu_out = res['fast1']
 296             print(f"expected {expected:x}, actual: {alu_out:x}")
 297             dut.assertEqual(expected, alu_out, msg)
 298
 299     def check_fast_spr2(dut, res, sim_o, msg):
 300         if 'fast2' in res:
 301             expected = sim_o['fast2']
 302             alu_out = res['fast2']
 303             print(f"expected {expected:x}, actual: {alu_out:x}")
 304             dut.assertEqual(expected, alu_out, msg)
 305
 306     def check_int_o1(dut, res, sim_o, msg):
 307         if 'o1' in res:
 308             expected = sim_o['o1']
 309             alu_out = res['o1']
 310             print(f"expected {expected:x}, actual: {alu_out:x}")
 311             dut.assertEqual(expected, alu_out, msg)
 312
 313     def check_int_o(dut, res, sim_o, msg):
 314         if 'o' in res:
 315             expected = sim_o['o']
 316             alu_out = res['o']
 317             print(f"expected {expected:x}, actual: {alu_out:x}")
 318             dut.assertEqual(expected, alu_out, msg)
 319
 320     def check_cr_a(dut, res, sim_o, msg):
 321         if 'cr_a' in res:
 322             cr_expected = sim_o['cr_a']
 323             cr_actual = res['cr_a']
 324             print ("CR", cr_expected, cr_actual)
 325             dut.assertEqual(cr_expected, cr_actual, msg)
 326
 327     def check_xer_ca(dut, res, sim_o, msg):
 328         if 'xer_ca' in res:
 329             ca_expected = sim_o['xer_ca']
 330             ca_actual = res['xer_ca']
 331             print ("CA", ca_expected, ca_actual)
 332             dut.assertEqual(ca_expected, ca_actual, msg)
 333
 334     def check_xer_ov(dut, res, sim_o, msg):
 335         if 'xer_ov' in res:
 336             ov_expected = sim_o['xer_ov']
 337             ov_actual = res['xer_ov']
 338             print ("OV", ov_expected, ov_actual)
 339             dut.assertEqual(ov_expected, ov_actual, msg)
 340
 341     def check_xer_so(dut, res, sim_o, msg):
 342         if 'xer_so' in res:
 343             so_expected = sim_o['xer_so']
 344             so_actual = res['xer_so']
 345             print ("SO", so_expected, so_actual)
 346             dut.assertEqual(so_expected, so_actual, msg)
 347