3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
6 from soc
.decoder
.power_enums
import XER_bits
, CryIn
7 from soc
.regfile
.util
import fast_reg_to_spr
# HACK!
11 def __init__(self
, program
, name
, regs
=None, sprs
=None, cr
=0, mem
=None,
14 self
.program
= program
31 def get_sim_fast_spr1(res
, sim
, dec2
):
32 fast1_en
= yield dec2
.e
.read_fast1
.ok
34 fast1_sel
= yield dec2
.e
.read_fast1
.data
35 spr1_sel
= fast_reg_to_spr(fast1_sel
)
36 spr1_data
= sim
.spr
[spr1_sel
].value
37 res
['spr1'] = spr1_data
39 def get_sim_fast_spr2(res
, sim
, dec2
):
40 fast2_en
= yield dec2
.e
.read_fast2
.ok
42 fast2_sel
= yield dec2
.e
.read_fast2
.data
43 spr2_sel
= fast_reg_to_spr(fast2_sel
)
44 spr2_data
= sim
.spr
[spr2_sel
].value
45 res
['spr2'] = spr2_data
47 def get_sim_cr_a(res
, sim
, dec2
):
48 cridx_ok
= yield dec2
.e
.read_cr1
.ok
50 cridx
= yield dec2
.e
.read_cr1
.data
51 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
53 def get_sim_int_ra(res
, sim
, dec2
):
54 # TODO: immediate RA zero
55 reg1_ok
= yield dec2
.e
.read_reg1
.ok
57 data1
= yield dec2
.e
.read_reg1
.data
58 res
['ra'] = sim
.gpr(data1
).value
60 def get_sim_int_rb(res
, sim
, dec2
):
61 reg2_ok
= yield dec2
.e
.read_reg2
.ok
63 data
= yield dec2
.e
.read_reg2
.data
64 res
['rb'] = sim
.gpr(data
).value
66 def get_sim_int_rc(res
, sim
, dec2
):
67 reg3_ok
= yield dec2
.e
.read_reg3
.ok
69 data
= yield dec2
.e
.read_reg3
.data
70 res
['rc'] = sim
.gpr(data
).value
72 def get_rd_sim_xer_ca(res
, sim
, dec2
):
73 cry_in
= yield dec2
.e
.input_carry
74 if cry_in
== CryIn
.CA
.value
:
75 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
76 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
77 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
79 def set_int_ra(alu
, dec2
, inp
):
80 # TODO: immediate RA zero.
82 yield alu
.p
.data_i
.ra
.eq(inp
['ra'])
84 yield alu
.p
.data_i
.ra
.eq(0)
86 def set_int_rb(alu
, dec2
, inp
):
87 yield alu
.p
.data_i
.rb
.eq(0)
89 yield alu
.p
.data_i
.rb
.eq(inp
['rb'])
90 # If there's an immediate, set the B operand to that
91 imm_ok
= yield dec2
.e
.imm_data
.imm_ok
93 data2
= yield dec2
.e
.imm_data
.imm
94 yield alu
.p
.data_i
.rb
.eq(data2
)
96 def set_int_rc(alu
, dec2
, inp
):
98 yield alu
.p
.data_i
.rc
.eq(inp
['rc'])
100 yield alu
.p
.data_i
.rc
.eq(0)
102 def set_xer_ca(alu
, dec2
, inp
):
104 yield alu
.p
.data_i
.xer_ca
.eq(inp
['xer_ca'])
105 print ("extra inputs: CA/32", bin(inp
['xer_ca']))
107 def set_xer_so(alu
, dec2
, inp
):
110 print ("extra inputs: so", so
)
111 yield alu
.p
.data_i
.xer_so
.eq(so
)
113 def set_fast_cia(alu
, dec2
, inp
):
115 yield alu
.p
.data_i
.cia
.eq(inp
['cia'])
117 def set_fast_spr1(alu
, dec2
, inp
):
119 yield alu
.p
.data_i
.spr1
.eq(inp
['spr1'])
121 def set_fast_spr2(alu
, dec2
, inp
):
123 yield alu
.p
.data_i
.spr2
.eq(inp
['spr2'])
125 def set_cr_a(alu
, dec2
, inp
):
127 yield alu
.p
.data_i
.cr_a
.eq(inp
['cr_a'])
129 def set_cr_b(alu
, dec2
, inp
):
131 yield alu
.p
.data_i
.cr_b
.eq(inp
['cr_b'])
133 def set_cr_c(alu
, dec2
, inp
):
135 yield alu
.p
.data_i
.cr_c
.eq(inp
['cr_c'])
137 def set_full_cr(alu
, dec2
, inp
):
139 yield alu
.p
.data_i
.full_cr
.eq(inp
['full_cr'])
141 yield alu
.p
.data_i
.full_cr
.eq(0)
143 def get_int_o(res
, alu
, dec2
):
144 out_reg_valid
= yield dec2
.e
.write_reg
.ok
146 res
['o'] = yield alu
.n
.data_o
.o
.data
148 def get_cr_a(res
, alu
, dec2
):
149 cridx_ok
= yield dec2
.e
.write_cr
.ok
151 res
['cr_a'] = yield alu
.n
.data_o
.cr0
.data
153 def get_xer_so(res
, alu
, dec2
):
154 oe
= yield dec2
.e
.oe
.oe
155 oe_ok
= yield dec2
.e
.oe
.ok
157 res
['xer_so'] = yield alu
.n
.data_o
.xer_so
.data
[0]
159 def get_xer_ov(res
, alu
, dec2
):
160 oe
= yield dec2
.e
.oe
.oe
161 oe_ok
= yield dec2
.e
.oe
.ok
163 res
['xer_ov'] = yield alu
.n
.data_o
.xer_ov
.data
165 def get_xer_ca(res
, alu
, dec2
):
166 cry_out
= yield dec2
.e
.output_carry
168 res
['xer_ca'] = yield alu
.n
.data_o
.xer_ca
.data
170 def get_sim_int_o(res
, sim
, dec2
):
171 out_reg_valid
= yield dec2
.e
.write_reg
.ok
173 write_reg_idx
= yield dec2
.e
.write_reg
.data
174 res
['o'] = sim
.gpr(write_reg_idx
).value
176 def get_wr_sim_cr_a(res
, sim
, dec2
):
177 cridx_ok
= yield dec2
.e
.write_cr
.ok
179 cridx
= yield dec2
.e
.write_cr
.data
180 res
['cr_a'] = sim
.crl
[cridx
].get_range().value
182 def get_wr_sim_xer_ca(res
, sim
, dec2
):
183 cry_out
= yield dec2
.e
.output_carry
185 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
186 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
187 res
['xer_ca'] = expected_carry |
(expected_carry32
<< 1)
189 def get_sim_xer_ov(res
, sim
, dec2
):
190 oe
= yield dec2
.e
.oe
.oe
191 oe_ok
= yield dec2
.e
.oe
.ok
193 expected_ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
194 expected_ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
195 res
['xer_ov'] = expected_ov |
(expected_ov32
<< 1)
197 def get_sim_xer_so(res
, sim
, dec2
):
198 oe
= yield dec2
.e
.oe
.oe
199 oe_ok
= yield dec2
.e
.oe
.ok
201 res
['xer_so'] = 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
203 def check_int_o(dut
, res
, sim_o
, msg
):
205 expected
= sim_o
['o']
207 print(f
"expected {expected:x}, actual: {alu_out:x}")
208 dut
.assertEqual(expected
, alu_out
, msg
)
210 def check_cr_a(dut
, res
, sim_o
, msg
):
212 cr_expected
= sim_o
['cr_a']
213 cr_actual
= res
['cr_a']
214 print ("CR", cr_expected
, cr_actual
)
215 dut
.assertEqual(cr_expected
, cr_actual
, msg
)
217 def check_xer_ca(dut
, res
, sim_o
, msg
):
219 ca_expected
= sim_o
['xer_ca']
220 ca_actual
= res
['xer_ca']
221 print ("CA", ca_expected
, ca_actual
)
222 dut
.assertEqual(ca_expected
, ca_actual
, msg
)
224 def check_xer_ov(dut
, res
, sim_o
, msg
):
226 ov_expected
= sim_o
['xer_ov']
227 ov_actual
= res
['xer_ov']
228 print ("OV", ov_expected
, ov_actual
)
229 dut
.assertEqual(ov_expected
, ov_actual
, msg
)
231 def check_xer_so(dut
, res
, sim_o
, msg
):
233 so_expected
= sim_o
['xer_so']
234 so_actual
= res
['xer_so']
235 print ("SO", so_expected
, so_actual
)
236 dut
.assertEqual(so_expected
, so_actual
, msg
)