src/soc/fu/test/common.py

   1 from soc.decoder.power_enums import XER_bits
   2
   3
   4 class TestCase:
   5     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
   6                        msr=0):
   7
   8         self.program = program
   9         self.name = name
  10
  11         if regs is None:
  12             regs = [0] * 32
  13         if sprs is None:
  14             sprs = {}
  15         if mem is None:
  16             mem = {}
  17         self.regs = regs
  18         self.sprs = sprs
  19         self.cr = cr
  20         self.mem = mem
  21         self.msr = msr
  22
  23 class ALUHelpers:
  24
  25     def set_int_ra(alu, dec2, inp):
  26         if 'ra' in inp:
  27             yield alu.p.data_i.ra.eq(inp['ra'])
  28         else:
  29             yield alu.p.data_i.ra.eq(0)
  30
  31     def set_int_rb(alu, dec2, inp):
  32         yield alu.p.data_i.rb.eq(0)
  33         if 'rb' in inp:
  34             yield alu.p.data_i.rb.eq(inp['rb'])
  35         # If there's an immediate, set the B operand to that
  36         imm_ok = yield dec2.e.imm_data.imm_ok
  37         if imm_ok:
  38             data2 = yield dec2.e.imm_data.imm
  39             yield alu.p.data_i.rb.eq(data2)
  40
  41     def set_int_rc(alu, dec2, inp):
  42         if 'rc' in inp:
  43             yield alu.p.data_i.rc.eq(inp['rc'])
  44         else:
  45             yield alu.p.data_i.rc.eq(0)
  46
  47     def set_xer_ca(alu, dec2, inp):
  48         if 'xer_ca' in inp:
  49             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
  50             print ("extra inputs: CA/32", bin(inp['xer_ca']))
  51
  52     def set_xer_so(alu, dec2, inp):
  53         if 'xer_so' in inp:
  54             so = inp['xer_so']
  55             print ("extra inputs: so", so)
  56             yield alu.p.data_i.xer_so.eq(so)
  57
  58     def set_fast_cia(alu, dec2, inp):
  59         if 'cia' in inp:
  60             yield alu.p.data_i.cia.eq(inp['cia'])
  61
  62     def set_fast_spr1(alu, dec2, inp):
  63         if 'spr1' in inp:
  64             yield alu.p.data_i.spr1.eq(inp['spr1'])
  65
  66     def set_fast_spr2(alu, dec2, inp):
  67         if 'spr2' in inp:
  68             yield alu.p.data_i.spr2.eq(inp['spr2'])
  69
  70     def set_cr_a(alu, dec2, inp):
  71         if 'cr_a' in inp:
  72             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
  73
  74     def set_cr_b(alu, dec2, inp):
  75         if 'cr_b' in inp:
  76             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
  77
  78     def set_cr_c(alu, dec2, inp):
  79         if 'cr_c' in inp:
  80             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
  81
  82     def set_full_cr(alu, dec2, inp):
  83         if 'full_cr' in inp:
  84             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
  85         else:
  86             yield alu.p.data_i.full_cr.eq(0)
  87
  88     def get_int_o(res, alu, dec2):
  89         out_reg_valid = yield dec2.e.write_reg.ok
  90         if out_reg_valid:
  91             res['o'] = yield alu.n.data_o.o.data
  92
  93     def get_cr_a(res, alu, dec2):
  94         cridx_ok = yield dec2.e.write_cr.ok
  95         if cridx_ok:
  96             res['cr_a'] = yield alu.n.data_o.cr0.data
  97
  98     def get_xer_so(res, alu, dec2):
  99         oe = yield dec2.e.oe.oe
 100         oe_ok = yield dec2.e.oe.ok
 101         if oe and oe_ok:
 102             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 103
 104     def get_xer_ov(res, alu, dec2):
 105         oe = yield dec2.e.oe.oe
 106         oe_ok = yield dec2.e.oe.ok
 107         if oe and oe_ok:
 108             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 109
 110     def get_xer_ca(res, alu, dec2):
 111         cry_out = yield dec2.e.output_carry
 112         if cry_out:
 113             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 114
 115     def get_sim_int_o(res, sim, dec2):
 116         out_reg_valid = yield dec2.e.write_reg.ok
 117         if out_reg_valid:
 118             write_reg_idx = yield dec2.e.write_reg.data
 119             res['o'] = sim.gpr(write_reg_idx).value
 120
 121     def get_sim_cr_a(res, sim, dec2):
 122         cridx_ok = yield dec2.e.write_cr.ok
 123         if cridx_ok:
 124             cridx = yield dec2.e.write_cr.data
 125             res['cr_a'] = sim.crl[cridx].get_range().value
 126
 127     def get_sim_xer_ca(res, sim, dec2):
 128         cry_out = yield dec2.e.output_carry
 129         if cry_out:
 130             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 131             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 132             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 133
 134     def get_sim_xer_ov(res, sim, dec2):
 135         oe = yield dec2.e.oe.oe
 136         oe_ok = yield dec2.e.oe.ok
 137         if oe and oe_ok:
 138             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 139             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 140             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 141
 142     def get_sim_xer_so(res, sim, dec2):
 143         oe = yield dec2.e.oe.oe
 144         oe_ok = yield dec2.e.oe.ok
 145         if oe and oe_ok:
 146             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 147
 148     def check_int_o(dut, res, sim_o, msg):
 149         if 'o' in res:
 150             expected = sim_o['o']
 151             alu_out = res['o']
 152             print(f"expected {expected:x}, actual: {alu_out:x}")
 153             dut.assertEqual(expected, alu_out, msg)
 154
 155     def check_cr_a(dut, res, sim_o, msg):
 156         if 'cr_a' in res:
 157             cr_expected = sim_o['cr_a']
 158             cr_actual = res['cr_a']
 159             print ("CR", cr_expected, cr_actual)
 160             dut.assertEqual(cr_expected, cr_actual, msg)
 161
 162     def check_xer_ca(dut, res, sim_o, msg):
 163         if 'xer_ca' in res:
 164             ca_expected = sim_o['xer_ca']
 165             ca_actual = res['xer_ca']
 166             print ("CA", ca_expected, ca_actual)
 167             dut.assertEqual(ca_expected, ca_actual, msg)
 168
 169     def check_xer_ov(dut, res, sim_o, msg):
 170         if 'xer_ov' in res:
 171             ov_expected = sim_o['xer_ov']
 172             ov_actual = res['xer_ov']
 173             print ("OV", ov_expected, ov_actual)
 174             dut.assertEqual(ov_expected, ov_actual, msg)
 175
 176     def check_xer_so(dut, res, sim_o, msg):
 177         if 'xer_so' in res:
 178             so_expected = sim_o['xer_so']
 179             so_actual = res['xer_so']
 180             print ("SO", so_expected, so_actual)
 181             dut.assertEqual(so_expected, so_actual, msg)
 182