src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8 from soc.regfile.regfiles import FastRegs
   9
  10
  11 class TestCase:
  12     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  13                        msr=0,
  14                        do_sim=True,
  15                        extra_break_addr=None):
  16
  17         self.program = program
  18         self.name = name
  19
  20         if regs is None:
  21             regs = [0] * 32
  22         if sprs is None:
  23             sprs = {}
  24         if mem is None:
  25             mem = {}
  26         self.regs = regs
  27         self.sprs = sprs
  28         self.cr = cr
  29         self.mem = mem
  30         self.msr = msr
  31         self.do_sim = do_sim
  32         self.extra_break_addr = extra_break_addr
  33
  34
  35 class ALUHelpers:
  36
  37     def get_sim_fast_reg(res, sim, dec2, reg, name):
  38         spr_sel = fast_reg_to_spr(reg)
  39         spr_data = sim.spr[spr_sel].value
  40         res[name] = spr_data
  41
  42     def get_sim_cia(res, sim, dec2):
  43         res['cia'] = sim.pc.CIA.value
  44
  45     # use this *after* the simulation has run a step (it returns CIA)
  46     def get_sim_nia(res, sim, dec2):
  47         res['nia'] = sim.pc.CIA.value
  48
  49     def get_sim_msr(res, sim, dec2):
  50         res['msr'] = sim.msr.value
  51
  52     def get_sim_slow_spr1(res, sim, dec2):
  53         spr1_en = yield dec2.e.read_spr1.ok
  54         if spr1_en:
  55             spr1_sel = yield dec2.e.read_spr1.data
  56             spr1_data = sim.spr[spr1_sel].value
  57             res['spr1'] = spr1_data
  58
  59     def get_sim_fast_spr1(res, sim, dec2):
  60         fast1_en = yield dec2.e.read_fast1.ok
  61         if fast1_en:
  62             fast1_sel = yield dec2.e.read_fast1.data
  63             spr1_sel = fast_reg_to_spr(fast1_sel)
  64             spr1_data = sim.spr[spr1_sel].value
  65             res['fast1'] = spr1_data
  66
  67     def get_sim_fast_spr2(res, sim, dec2):
  68         fast2_en = yield dec2.e.read_fast2.ok
  69         if fast2_en:
  70             fast2_sel = yield dec2.e.read_fast2.data
  71             spr2_sel = fast_reg_to_spr(fast2_sel)
  72             spr2_data = sim.spr[spr2_sel].value
  73             res['fast2'] = spr2_data
  74
  75     def get_sim_cr_a(res, sim, dec2):
  76         cridx_ok = yield dec2.e.read_cr1.ok
  77         if cridx_ok:
  78             cridx = yield dec2.e.read_cr1.data
  79             res['cr_a'] = sim.crl[cridx].get_range().value
  80
  81     def get_sim_int_ra(res, sim, dec2):
  82         # TODO: immediate RA zero
  83         reg1_ok = yield dec2.e.read_reg1.ok
  84         if reg1_ok:
  85             data1 = yield dec2.e.read_reg1.data
  86             res['ra'] = sim.gpr(data1).value
  87
  88     def get_sim_int_rb(res, sim, dec2):
  89         reg2_ok = yield dec2.e.read_reg2.ok
  90         if reg2_ok:
  91             data = yield dec2.e.read_reg2.data
  92             res['rb'] = sim.gpr(data).value
  93
  94     def get_sim_int_rc(res, sim, dec2):
  95         reg3_ok = yield dec2.e.read_reg3.ok
  96         if reg3_ok:
  97             data = yield dec2.e.read_reg3.data
  98             res['rc'] = sim.gpr(data).value
  99
 100     def get_rd_sim_xer_ca(res, sim, dec2):
 101         cry_in = yield dec2.e.do.input_carry
 102         xer_in = yield dec2.e.xer_in
 103         if xer_in or cry_in == CryIn.CA.value:
 104             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 105             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 106             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 107
 108     def set_int_ra(alu, dec2, inp):
 109         # TODO: immediate RA zero.
 110         if 'ra' in inp:
 111             yield alu.p.data_i.ra.eq(inp['ra'])
 112         else:
 113             yield alu.p.data_i.ra.eq(0)
 114
 115     def set_int_rb(alu, dec2, inp):
 116         yield alu.p.data_i.rb.eq(0)
 117         if 'rb' in inp:
 118             yield alu.p.data_i.rb.eq(inp['rb'])
 119         # If there's an immediate, set the B operand to that
 120         imm_ok = yield dec2.e.do.imm_data.imm_ok
 121         if imm_ok:
 122             data2 = yield dec2.e.do.imm_data.imm
 123             yield alu.p.data_i.rb.eq(data2)
 124
 125     def set_int_rc(alu, dec2, inp):
 126         if 'rc' in inp:
 127             yield alu.p.data_i.rc.eq(inp['rc'])
 128         else:
 129             yield alu.p.data_i.rc.eq(0)
 130
 131     def set_xer_ca(alu, dec2, inp):
 132         if 'xer_ca' in inp:
 133             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 134             print ("extra inputs: CA/32", bin(inp['xer_ca']))
 135
 136     def set_xer_ov(alu, dec2, inp):
 137         if 'xer_ov' in inp:
 138             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 139             print ("extra inputs: OV/32", bin(inp['xer_ov']))
 140
 141     def set_xer_so(alu, dec2, inp):
 142         if 'xer_so' in inp:
 143             so = inp['xer_so']
 144             print ("extra inputs: so", so)
 145             yield alu.p.data_i.xer_so.eq(so)
 146
 147     def set_msr(alu, dec2, inp):
 148         print ("TODO: deprecate set_msr")
 149         if 'msr' in inp:
 150             yield alu.p.data_i.msr.eq(inp['msr'])
 151
 152     def set_cia(alu, dec2, inp):
 153         print ("TODO: deprecate set_cia")
 154         if 'cia' in inp:
 155             yield alu.p.data_i.cia.eq(inp['cia'])
 156
 157     def set_slow_spr1(alu, dec2, inp):
 158         if 'spr1' in inp:
 159             yield alu.p.data_i.spr1.eq(inp['spr1'])
 160
 161     def set_slow_spr2(alu, dec2, inp):
 162         if 'spr2' in inp:
 163             yield alu.p.data_i.spr2.eq(inp['spr2'])
 164
 165     def set_fast_spr1(alu, dec2, inp):
 166         if 'fast1' in inp:
 167             yield alu.p.data_i.fast1.eq(inp['fast1'])
 168
 169     def set_fast_spr2(alu, dec2, inp):
 170         if 'fast2' in inp:
 171             yield alu.p.data_i.fast2.eq(inp['fast2'])
 172
 173     def set_cr_a(alu, dec2, inp):
 174         if 'cr_a' in inp:
 175             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 176
 177     def set_cr_b(alu, dec2, inp):
 178         if 'cr_b' in inp:
 179             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 180
 181     def set_cr_c(alu, dec2, inp):
 182         if 'cr_c' in inp:
 183             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 184
 185     def set_full_cr(alu, dec2, inp):
 186         if 'full_cr' in inp:
 187             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 188         else:
 189             yield alu.p.data_i.full_cr.eq(0)
 190
 191     def get_slow_spr1(res, alu, dec2):
 192         spr1_valid = yield alu.n.data_o.spr1.ok
 193         if spr1_valid:
 194             res['spr1'] = yield alu.n.data_o.spr1.data
 195
 196     def get_slow_spr2(res, alu, dec2):
 197         spr2_valid = yield alu.n.data_o.spr2.ok
 198         if spr2_valid:
 199             res['spr2'] = yield alu.n.data_o.spr2.data
 200
 201     def get_fast_spr1(res, alu, dec2):
 202         spr1_valid = yield alu.n.data_o.fast1.ok
 203         if spr1_valid:
 204             res['fast1'] = yield alu.n.data_o.fast1.data
 205
 206     def get_fast_spr2(res, alu, dec2):
 207         spr2_valid = yield alu.n.data_o.fast2.ok
 208         if spr2_valid:
 209             res['fast2'] = yield alu.n.data_o.fast2.data
 210
 211     def get_cia(res, alu, dec2):
 212         res['cia'] = yield alu.p.data_i.cia
 213
 214     def get_nia(res, alu, dec2):
 215         nia_valid = yield alu.n.data_o.nia.ok
 216         if nia_valid:
 217             res['nia'] = yield alu.n.data_o.nia.data
 218
 219     def get_msr(res, alu, dec2):
 220         msr_valid = yield alu.n.data_o.msr.ok
 221         if msr_valid:
 222             res['msr'] = yield alu.n.data_o.msr.data
 223
 224     def get_int_o1(res, alu, dec2):
 225         out_reg_valid = yield dec2.e.write_ea.ok
 226         if out_reg_valid:
 227             res['o1'] = yield alu.n.data_o.o1.data
 228
 229     def get_int_o(res, alu, dec2):
 230         out_reg_valid = yield dec2.e.write_reg.ok
 231         if out_reg_valid:
 232             res['o'] = yield alu.n.data_o.o.data
 233
 234     def get_cr_a(res, alu, dec2):
 235         cridx_ok = yield dec2.e.write_cr.ok
 236         if cridx_ok:
 237             res['cr_a'] = yield alu.n.data_o.cr0.data
 238
 239     def get_xer_so(res, alu, dec2):
 240         oe = yield dec2.e.do.oe.oe
 241         oe_ok = yield dec2.e.do.oe.ok
 242         xer_out = yield dec2.e.xer_out
 243         if not (yield alu.n.data_o.xer_so.ok):
 244             return
 245         if xer_out or (oe and oe_ok):
 246             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 247
 248     def get_xer_ov(res, alu, dec2):
 249         oe = yield dec2.e.do.oe.oe
 250         oe_ok = yield dec2.e.do.oe.ok
 251         xer_out = yield dec2.e.xer_out
 252         if not (yield alu.n.data_o.xer_ov.ok):
 253             return
 254         if xer_out or (oe and oe_ok):
 255             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 256
 257     def get_xer_ca(res, alu, dec2):
 258         cry_out = yield dec2.e.do.output_carry
 259         xer_out = yield dec2.e.xer_out
 260         if not (yield alu.n.data_o.xer_ca.ok):
 261             return
 262         if xer_out or (cry_out):
 263             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 264
 265     def get_sim_int_o(res, sim, dec2):
 266         out_reg_valid = yield dec2.e.write_reg.ok
 267         if out_reg_valid:
 268             write_reg_idx = yield dec2.e.write_reg.data
 269             res['o'] = sim.gpr(write_reg_idx).value
 270
 271     def get_sim_int_o1(res, sim, dec2):
 272         out_reg_valid = yield dec2.e.write_ea.ok
 273         if out_reg_valid:
 274             write_reg_idx = yield dec2.e.write_ea.data
 275             res['o1'] = sim.gpr(write_reg_idx).value
 276
 277     def get_wr_sim_cr_a(res, sim, dec2):
 278         cridx_ok = yield dec2.e.write_cr.ok
 279         if cridx_ok:
 280             cridx = yield dec2.e.write_cr.data
 281             res['cr_a'] = sim.crl[cridx].get_range().value
 282
 283     def get_wr_fast_spr2(res, sim, dec2):
 284         ok = yield dec2.e.write_fast2.ok
 285         if ok:
 286             spr_num = yield dec2.e.write_fast2.data
 287             spr_num = fast_reg_to_spr(spr_num)
 288             spr_name = spr_dict[spr_num].SPR
 289             res['fast2'] = sim.spr[spr_name].value
 290
 291     def get_wr_fast_spr1(res, sim, dec2):
 292         ok = yield dec2.e.write_fast1.ok
 293         if ok:
 294             spr_num = yield dec2.e.write_fast1.data
 295             spr_num = fast_reg_to_spr(spr_num)
 296             spr_name = spr_dict[spr_num].SPR
 297             res['fast1'] = sim.spr[spr_name].value
 298
 299     def get_wr_slow_spr1(res, sim, dec2):
 300         ok = yield dec2.e.write_spr.ok
 301         if ok:
 302             spr_num = yield dec2.e.write_spr.data
 303             spr_name = spr_dict[spr_num].SPR
 304             res['spr1'] = sim.spr[spr_name].value
 305
 306     def get_wr_sim_xer_ca(res, sim, dec2):
 307         #if not (yield alu.n.data_o.xer_ca.ok):
 308         #    return
 309         cry_out = yield dec2.e.do.output_carry
 310         xer_out = yield dec2.e.xer_out
 311         if cry_out or xer_out:
 312             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 313             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 314             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 315
 316     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 317         oe = yield dec2.e.do.oe.oe
 318         oe_ok = yield dec2.e.do.oe.ok
 319         xer_out = yield dec2.e.xer_out
 320         print ("get_wr_sim_xer_ov", xer_out)
 321         if not (yield alu.n.data_o.xer_ov.ok):
 322             return
 323         if xer_out or (oe and oe_ok):
 324             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 325             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 326             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 327
 328     def get_wr_sim_xer_so(res, sim, alu, dec2):
 329         oe = yield dec2.e.do.oe.oe
 330         oe_ok = yield dec2.e.do.oe.ok
 331         xer_out = yield dec2.e.xer_out
 332         if not (yield alu.n.data_o.xer_so.ok):
 333             return
 334         if xer_out or (oe and oe_ok):
 335             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 336
 337     def get_sim_xer_ov(res, sim, dec2):
 338         oe = yield dec2.e.do.oe.oe
 339         oe_ok = yield dec2.e.do.oe.ok
 340         xer_in = yield dec2.e.xer_in
 341         print ("get_sim_xer_ov", xer_in)
 342         if xer_in or (oe and oe_ok):
 343             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 344             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 345             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 346
 347     def get_sim_xer_so(res, sim, dec2):
 348         oe = yield dec2.e.do.oe.oe
 349         oe_ok = yield dec2.e.do.oe.ok
 350         xer_in = yield dec2.e.xer_in
 351         if xer_in or (oe and oe_ok):
 352             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 353
 354     def check_slow_spr1(dut, res, sim_o, msg):
 355         if 'spr1' in res:
 356             expected = sim_o['spr1']
 357             alu_out = res['spr1']
 358             print(f"expected {expected:x}, actual: {alu_out:x}")
 359             dut.assertEqual(expected, alu_out, msg)
 360
 361     def check_fast_spr1(dut, res, sim_o, msg):
 362         if 'fast1' in res:
 363             expected = sim_o['fast1']
 364             alu_out = res['fast1']
 365             print(f"expected {expected:x}, actual: {alu_out:x}")
 366             dut.assertEqual(expected, alu_out, msg)
 367
 368     def check_fast_spr2(dut, res, sim_o, msg):
 369         if 'fast2' in res:
 370             expected = sim_o['fast2']
 371             alu_out = res['fast2']
 372             print(f"expected {expected:x}, actual: {alu_out:x}")
 373             dut.assertEqual(expected, alu_out, msg)
 374
 375     def check_int_o1(dut, res, sim_o, msg):
 376         if 'o1' in res:
 377             expected = sim_o['o1']
 378             alu_out = res['o1']
 379             print(f"expected {expected:x}, actual: {alu_out:x}")
 380             dut.assertEqual(expected, alu_out, msg)
 381
 382     def check_int_o(dut, res, sim_o, msg):
 383         if 'o' in res:
 384             expected = sim_o['o']
 385             alu_out = res['o']
 386             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 387             dut.assertEqual(expected, alu_out, msg)
 388
 389     def check_msr(dut, res, sim_o, msg):
 390         if 'msr' in res:
 391             expected = sim_o['msr']
 392             alu_out = res['msr']
 393             print(f"expected {expected:x}, actual: {alu_out:x}")
 394             dut.assertEqual(expected, alu_out, msg)
 395
 396     def check_nia(dut, res, sim_o, msg):
 397         if 'nia' in res:
 398             expected = sim_o['nia']
 399             alu_out = res['nia']
 400             print(f"expected {expected:x}, actual: {alu_out:x}")
 401             dut.assertEqual(expected, alu_out, msg)
 402
 403     def check_cr_a(dut, res, sim_o, msg):
 404         if 'cr_a' in res:
 405             cr_expected = sim_o['cr_a']
 406             cr_actual = res['cr_a']
 407             print ("CR", cr_expected, cr_actual)
 408             dut.assertEqual(cr_expected, cr_actual, msg)
 409
 410     def check_xer_ca(dut, res, sim_o, msg):
 411         if 'xer_ca' in res:
 412             ca_expected = sim_o['xer_ca']
 413             ca_actual = res['xer_ca']
 414             print ("CA", ca_expected, ca_actual)
 415             dut.assertEqual(ca_expected, ca_actual, msg)
 416
 417     def check_xer_ov(dut, res, sim_o, msg):
 418         if 'xer_ov' in res:
 419             ov_expected = sim_o['xer_ov']
 420             ov_actual = res['xer_ov']
 421             print ("OV", ov_expected, ov_actual)
 422             dut.assertEqual(ov_expected, ov_actual, msg)
 423
 424     def check_xer_so(dut, res, sim_o, msg):
 425         if 'xer_so' in res:
 426             so_expected = sim_o['xer_so']
 427             so_actual = res['xer_so']
 428             print ("SO", so_expected, so_actual)
 429             dut.assertEqual(so_expected, so_actual, msg)
 430