3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
5 * https://libre-soc.org/openpower/isa/fixedtrap/
8 from nmigen
import (Module
, Signal
, Cat
, Mux
, Const
, signed
)
9 from nmutil
.pipemodbase
import PipeModBase
10 from nmutil
.extend
import exts
11 from soc
.fu
.trap
.pipe_data
import TrapInputData
, TrapOutputData
12 from soc
.fu
.branch
.main_stage
import br_ext
13 from soc
.decoder
.power_enums
import InternalOp
15 from soc
.decoder
.power_fields
import DecodeFields
16 from soc
.decoder
.power_fieldsn
import SignalBitRange
19 # Listed in V3.0B Book III Chap 4.2.1
21 MSR_SF
= (63 - 0) # Sixty-Four bit mode
22 MSR_HV
= (63 - 3) # Hypervisor state
23 MSR_S
= (63 - 41) # Secure state
24 MSR_EE
= (63 - 48) # External interrupt Enable
25 MSR_PR
= (63 - 49) # PRoblem state
26 MSR_FP
= (63 - 50) # FP available
27 MSR_ME
= (63 - 51) # Machine Check int enable
28 MSR_IR
= (63 - 58) # Instruction Relocation
29 MSR_DR
= (63 - 59) # Data Relocation
30 MSR_PMM
= (63 - 60) # Performance Monitor Mark
31 MSR_RI
= (63 - 62) # Recoverable Interrupt
32 MSR_LE
= (63 - 63) # Little Endian
34 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
36 # note that these correspond to trap_input_record.traptype bits 0,1,2,3
39 PI_FP
= (63 - 43) # 1 if FP exception
40 PI_PRIV
= (63 - 45) # 1 if privileged interrupt
41 PI_TRAP
= (63 - 46) # 1 if exception is "trap" type
42 PI_ADR
= (63 - 47) # 0 if SRR0 = address of instruction causing exception
45 def msr_copy(msr_o
, msr_i
, zero_me
=True):
48 -- Defined MSR bits are classified as either full func-
49 -- tion or partial function. Full function MSR bits are
50 -- saved in SRR1 or HSRR1 when an interrupt other
51 -- than a System Call Vectored interrupt occurs and
52 -- restored by rfscv, rfid, or hrfid, while partial func-
53 -- tion MSR bits are not saved or restored.
54 -- Full function MSR bits lie in the range 0:32, 37:41, and
55 -- 48:63, and partial function MSR bits lie in the range
56 -- 33:36 and 42:47. (Note this is IBM bit numbering).
57 msr_out := (others => '0');
58 msr_out(63 downto 31) := msr(63 downto 31);
59 msr_out(26 downto 22) := msr(26 downto 22);
60 msr_out(15 downto 0) := msr(15 downto 0);
65 for stt
, end
in [(0,16), (22, 27), (31, 64)]:
66 l
.append(msr_o
[stt
:end
].eq(msr_i
[stt
:end
]))
70 def msr_check_pr(m
, msr_o
):
71 """msr_check_pr: checks "problem state"
74 with m
.If(msrdata
[MSR_PR
]):
75 comb
+= msr
[MSR_EE
].eq(1) # set external interrupt bit
76 comb
+= msr
[MSR_IR
].eq(1) # set instruction relocation bit
77 comb
+= msr
[MSR_DR
].eq(1) # set data relocation bit
80 class TrapMainStage(PipeModBase
):
81 def __init__(self
, pspec
):
82 super().__init
__(pspec
, "main")
83 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
84 self
.fields
.create_specs()
86 def trap(self
, m
, return_addr
, trap_addr
):
87 """trap """ # TODO add descriptive docstring
89 nia_o
, srr0_o
, srr1_o
= self
.o
.nia
, self
.o
.srr0
, self
.o
.srr1
92 comb
+= nia_o
.data
.eq(trap_addr
)
93 comb
+= nia_o
.ok
.eq(1)
95 # addr to begin from on return
96 comb
+= srr0_o
.data
.eq(return_addr
)
97 comb
+= srr0_o
.ok
.eq(1)
99 # take a copy of the current MSR in SRR1
100 comb
+= msr_copy(srr1_o
.data
, msr_i
) # old MSR
101 comb
+= srr1_o
.ok
.eq(1)
104 return TrapInputData(self
.pspec
)
107 return TrapOutputData(self
.pspec
)
109 def elaborate(self
, platform
):
114 # convenience variables
115 a_i
, b_i
, cia_i
, msr_i
= self
.i
.a
, self
.i
.b
, self
.i
.cia
, self
.i
.msr
116 o
, msr_o
, nia_o
= self
.o
.o
, self
.o
.msr
, self
.o
.nia
117 srr0_o
, srr1_o
= self
.o
.srr0
, self
.o
.srr1
119 # take copy of D-Form TO field
120 i_fields
= self
.fields
.FormD
121 to
= Signal(i_fields
.TO
[0:-1].shape())
122 comb
+= to
.eq(i_fields
.TO
[0:-1])
124 # signed/unsigned temporaries for RA and RB
125 a_s
= Signal(signed(64), reset_less
=True)
126 b_s
= Signal(signed(64), reset_less
=True)
128 a
= Signal(64, reset_less
=True)
129 b
= Signal(64, reset_less
=True)
131 # set up A and B comparison (truncate/sign-extend if 32 bit)
132 with m
.If(op
.is_32bit
):
133 comb
+= a_s
.eq(exts(a_i
, 32, 64))
134 comb
+= b_s
.eq(exts(b_i
, 32, 64))
135 comb
+= a
.eq(a_i
[0:32])
136 comb
+= b
.eq(b_i
[0:32])
143 # establish comparison bits
144 lt_s
= Signal(reset_less
=True)
145 gt_s
= Signal(reset_less
=True)
146 lt_u
= Signal(reset_less
=True)
147 gt_u
= Signal(reset_less
=True)
148 equal
= Signal(reset_less
=True)
150 comb
+= lt_s
.eq(a_s
< b_s
)
151 comb
+= gt_s
.eq(a_s
> b_s
)
152 comb
+= lt_u
.eq(a
< b
)
153 comb
+= gt_u
.eq(a
> b
)
154 comb
+= equal
.eq(a
== b
)
156 # They're in reverse bit order because POWER.
157 # Check V3.0B Book 1, Appendix C.6 for chart
158 trap_bits
= Signal(5)
159 comb
+= trap_bits
.eq(Cat(gt_u
, lt_u
, equal
, gt_s
, lt_s
))
161 # establish if the trap should go ahead (any tests requested in TO)
162 should_trap
= Signal()
163 comb
+= should_trap
.eq((trap_bits
& to
).any())
165 # TODO: some #defines for the bits n stuff.
168 with m
.Case(InternalOp
.OP_TRAP
):
169 # trap instructions (tw, twi, td, tdi)
170 with m
.If(should_trap
):
171 # generate trap-type program interrupt
172 self
.trap(0x700, cia_i
)
173 # set bit 46 to say trap occurred (see 3.0B Book III 7.5.9)
174 comb
+= srr1_o
.data
[PI_TRAP
].eq(1)
177 with m
.Case(InternalOp
.OP_MTMSR
):
178 L
= self
.fields
.FormX
.L
[0:-1] # X-Form field L
180 # just update EE and RI
181 comb
+= msr_o
.data
[MSR_EE
].eq(a_i
[MSR_EE
])
182 comb
+= msr_o
.data
[MSR_RI
].eq(a_i
[MSR_RI
])
184 # Architecture says to leave out bits 3 (HV), 51 (ME)
185 # and 63 (LE) (IBM bit numbering)
186 for stt
, end
in [(1,12), (13, 60), (61, 64)]:
187 comb
+= msr_o
.data
[stt
:end
].eq(a_i
[stt
:end
])
188 msr_check_pr(m
, msr_o
.data
)
189 comb
+= msr_o
.ok
.eq(1)
192 with m
.Case(InternalOp
.OP_MFMSR
):
193 # TODO: some of the bits need zeroing? apparently not
194 comb
+= o
.data
.eq(msr_i
)
197 with m
.Case(InternalOp
.OP_RFID
):
198 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
199 # XXX f_out.priv_mode <= not b_in(MSR_PR);
201 # return addr was in srr0
202 comb
+= nia_o
.data
.eq(br_ext(srr0_i
[2:]))
203 comb
+= nia_o
.ok
.eq(1)
205 comb
+= msr_copy(msr_o
.data
, srr1_i
, zero_me
=False) # don't zero
206 msr_check_pr(m
, msr_o
.data
)
207 comb
+= msr_o
.ok
.eq(1)
209 with m
.Case(InternalOp
.OP_SC
):
210 # TODO: scv must generate illegal instruction. this is
211 # the decoder's job, not ours, here.
213 # jump to the trap address, return at cia+4
214 self
.trap(0xc00, cia_i
+4)
217 #with m.Case(InternalOp.OP_ADDPCIS):
220 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)