3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
5 * https://libre-soc.org/openpower/isa/fixedtrap/
8 from nmigen
import (Module
, Signal
, Cat
, Mux
, Const
, signed
)
9 from nmutil
.pipemodbase
import PipeModBase
10 from nmutil
.extend
import exts
11 from soc
.fu
.trap
.pipe_data
import TrapInputData
, TrapOutputData
12 from soc
.decoder
.power_enums
import InternalOp
14 from soc
.decoder
.power_fields
import DecodeFields
15 from soc
.decoder
.power_fieldsn
import SignalBitRange
17 # TODO at some point move these to their own module (for use elsewhere)
18 # TODO: turn these into python constants (just "MSR_SF = 63-0 # comment" etc.)
20 Listed in V3.0B Book III Chap 4.2.1
22 constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
23 constant MSR_HV : integer := (63 - 3); -- Hypervisor state
24 constant MSR_S : integer := (63 - 41); -- Secure state
25 constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
26 constant MSR_PR : integer := (63 - 49); -- PRoblem state
27 constant MSR_FP : integer := (63 - 50); -- FP available
28 constant MSR_ME : integer := (63 - 51); -- Machine Check int enable
29 constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
30 constant MSR_DR : integer := (63 - 59); -- Data Relocation
31 constant MSR_PMM : integer := (63 - 60); -- Performance Monitor Mark
32 constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
33 constant MSR_LE : integer := (63 - 63); -- Little Endian
36 class TrapMainStage(PipeModBase
):
37 def __init__(self
, pspec
):
38 super().__init
__(pspec
, "main")
39 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
40 self
.fields
.create_specs()
43 return TrapInputData(self
.pspec
)
46 return TrapOutputData(self
.pspec
)
48 def elaborate(self
, platform
):
52 a_i
, b_i
= self
.i
.a
, self
.i
.b
54 # take copy of D-Form TO field
55 i_fields
= self
.fields
.FormD
56 to
= Signal(i_fields
.TO
[0:-1].shape())
57 comb
+= to
.eq(i_fields
.TO
[0:-1])
59 # signed/unsigned temporaries for RA and RB
60 a_s
= Signal(signed(64), reset_less
=True)
61 b_s
= Signal(signed(64), reset_less
=True)
63 a
= Signal(64, reset_less
=True)
64 b
= Signal(64, reset_less
=True)
66 # set up A and B comparison (truncate/sign-extend if 32 bit)
67 with m
.If(op
.is_32bit
):
68 comb
+= a_s
.eq(exts(a_i
, 32, 64))
69 comb
+= b_s
.eq(exts(b_i
, 32, 64))
70 comb
+= a
.eq(a_i
[0:32])
71 comb
+= b
.eq(b_i
[0:32])
78 # establish comparison bits
79 lt_s
= Signal(reset_less
=True)
80 gt_s
= Signal(reset_less
=True)
81 lt_u
= Signal(reset_less
=True)
82 gt_u
= Signal(reset_less
=True)
83 equal
= Signal(reset_less
=True)
85 comb
+= lt_s
.eq(a_s
< b_s
)
86 comb
+= gt_s
.eq(a_s
> b_s
)
87 comb
+= lt_u
.eq(a
< b
)
88 comb
+= gt_u
.eq(a
> b
)
89 comb
+= equal
.eq(a
== b
)
91 # They're in reverse bit order because POWER.
92 # Check V3.0B Book 1, Appendix C.6 for chart
94 comb
+= trap_bits
.eq(Cat(gt_u
, lt_u
, equal
, gt_s
, lt_s
))
96 # establish if the trap should go ahead (any tests requested in TO)
97 should_trap
= Signal()
98 comb
+= should_trap
.eq((trap_bits
& to
).any())
100 # TODO: some #defines for the bits n stuff.
103 with m
.Case(InternalOp
.OP_TRAP
):
105 -- trap instructions (tw, twi, td, tdi)
106 if or (trapval and insn_to(e_in.insn)) = '1' then
107 -- generate trap-type program interrupt
109 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
110 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
111 -- set bit 46 to say trap occurred
112 ctrl_tmp.srr1(63 - 46) <= '1';
114 with m
.If(should_trap
):
115 comb
+= self
.o
.nia
.data
.eq(0x700) # trap address
116 comb
+= self
.o
.nia
.ok
.eq(1)
117 comb
+= self
.o
.srr1
.data
.eq(self
.i
.msr
) # old MSR
118 comb
+= self
.o
.srr1
.data
[63-46].eq(1) # XXX which bit?
119 comb
+= self
.o
.srr1
.ok
.eq(1)
120 comb
+= self
.o
.srr0
.data
.eq(self
.i
.cia
) # old PC
121 comb
+= self
.o
.srr0
.ok
.eq(1)
124 with m
.Case(InternalOp
.OP_MTMSR
):
125 # TODO: some of the bits need zeroing?
127 if e_in.insn(16) = '1' then <-- this is X-form field "L".
128 -- just update EE and RI
129 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
130 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
132 -- Architecture says to leave out bits 3 (HV), 51 (ME)
133 -- and 63 (LE) (IBM bit numbering)
134 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
135 ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
136 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
137 if c_in(MSR_PR) = '1' then
138 ctrl_tmp.msr(MSR_EE) <= '1';
139 ctrl_tmp.msr(MSR_IR) <= '1';
140 ctrl_tmp.msr(MSR_DR) <= '1';
142 # TODO translate this:
143 # L = self.fields.FormXL.L[0:-1]
144 # if e_in.insn(16) = '1' then <-- this is X-form field "L".
145 # -- just update EE and RI
146 # ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
147 # ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
149 for stt
, end
in [(1,12), (13, 60), (61, 64)]:
150 comb
+= self
.o
.msr
.data
[stt
:end
].eq(a
[stt
:end
])
151 with m
.If(a
[MSR_PR
]):
152 self
.o
.msr
[MSR_EE
].eq(1)
153 self
.o
.msr
[MSR_IR
].eq(1)
154 self
.o
.msr
[MSR_DR
].eq(1)
155 comb
+= self
.o
.msr
.ok
.eq(1)
158 with m
.Case(InternalOp
.OP_MFMSR
):
159 # TODO: some of the bits need zeroing? apparently not
165 comb
+= self
.o
.o
.data
.eq(self
.i
.msr
)
166 comb
+= self
.o
.o
.ok
.eq(1)
168 with m
.Case(InternalOp
.OP_RFID
):
170 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
171 # XXX f_out.priv_mode <= not b_in(MSR_PR);
172 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
173 -- Can't use msr_copy here because the partial function MSR
174 -- bits should be left unchanged, not zeroed.
175 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
176 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
177 ctrl_tmp.msr(15 downto 0) <= b_in(15 downto 0);
178 if b_in(MSR_PR) = '1' then
179 ctrl_tmp.msr(MSR_EE) <= '1';
180 ctrl_tmp.msr(MSR_IR) <= '1';
181 ctrl_tmp.msr(MSR_DR) <= '1';
184 # TODO translate this, import and use br_ext from branch stage
185 # f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
186 for stt
, end
in [(0,16), (22, 27), (31, 64)]:
187 comb
+= self
.o
.msr
.data
[stt
:end
].eq(a
[stt
:end
])
188 with m
.If(a
[MSR_PR
]):
189 self
.o
.msr
[MSR_EE
].eq(1)
190 self
.o
.msr
[MSR_IR
].eq(1)
191 self
.o
.msr
[MSR_DR
].eq(1)
192 comb
+= self
.o
.msr
.ok
.eq(1)
195 with m
.Case(InternalOp
.OP_SC
):
197 # TODO: scv must generate illegal instruction. this is
198 # the decoder's job, not ours, here.
199 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
200 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
202 comb
+= self
.o
.nia
.eq(0xC00) # trap address
203 comb
+= self
.o
.nia
.ok
.eq(1)
204 # TODO translate this line: ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
205 comb
+= self
.o
.srr1
.ok
.eq(1)
207 #with m.Case(InternalOp.OP_ADDPCIS):
210 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)