src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.fu.branch.main_stage import br_ext
  13 from soc.decoder.power_enums import InternalOp
  14
  15 from soc.decoder.power_fields import DecodeFields
  16 from soc.decoder.power_fieldsn import SignalBitRange
  17
  18
  19 # Listed in V3.0B Book III Chap 4.2.1
  20 # MSR bit numbers
  21 MSR_SF  = (63 - 0)     # Sixty-Four bit mode
  22 MSR_HV  = (63 - 3)     # Hypervisor state
  23 MSR_S   = (63 - 41)    # Secure state
  24 MSR_EE  = (63 - 48)    # External interrupt Enable
  25 MSR_PR  = (63 - 49)    # PRoblem state
  26 MSR_FP  = (63 - 50)    # FP available
  27 MSR_ME  = (63 - 51)    # Machine Check int enable
  28 MSR_IR  = (63 - 58)    # Instruction Relocation
  29 MSR_DR  = (63 - 59)    # Data Relocation
  30 MSR_PMM = (63 - 60)    # Performance Monitor Mark
  31 MSR_RI  = (63 - 62)    # Recoverable Interrupt
  32 MSR_LE  = (63 - 63)    # Little Endian
  33
  34
  35 class TrapMainStage(PipeModBase):
  36     def __init__(self, pspec):
  37         super().__init__(pspec, "main")
  38         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  39         self.fields.create_specs()
  40
  41     def ispec(self):
  42         return TrapInputData(self.pspec)
  43
  44     def ospec(self):
  45         return TrapOutputData(self.pspec)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         comb = m.d.comb
  50         op = self.i.ctx.op
  51
  52         # convenience variables
  53         a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
  54         o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
  55         srr0_o, srr1_o = self.o.srr0, self.o.srr1
  56
  57         # take copy of D-Form TO field
  58         i_fields = self.fields.FormD
  59         to = Signal(i_fields.TO[0:-1].shape())
  60         comb += to.eq(i_fields.TO[0:-1])
  61
  62         # signed/unsigned temporaries for RA and RB
  63         a_s = Signal(signed(64), reset_less=True)
  64         b_s = Signal(signed(64), reset_less=True)
  65
  66         a = Signal(64, reset_less=True)
  67         b = Signal(64, reset_less=True)
  68
  69         # set up A and B comparison (truncate/sign-extend if 32 bit)
  70         with m.If(op.is_32bit):
  71             comb += a_s.eq(exts(a_i, 32, 64))
  72             comb += b_s.eq(exts(b_i, 32, 64))
  73             comb += a.eq(a_i[0:32])
  74             comb += b.eq(b_i[0:32])
  75         with m.Else():
  76             comb += a_s.eq(a_i)
  77             comb += b_s.eq(b_i)
  78             comb += a.eq(a_i)
  79             comb += b.eq(b_i)
  80
  81         # establish comparison bits
  82         lt_s = Signal(reset_less=True)
  83         gt_s = Signal(reset_less=True)
  84         lt_u = Signal(reset_less=True)
  85         gt_u = Signal(reset_less=True)
  86         equal = Signal(reset_less=True)
  87
  88         comb += lt_s.eq(a_s < b_s)
  89         comb += gt_s.eq(a_s > b_s)
  90         comb += lt_u.eq(a < b)
  91         comb += gt_u.eq(a > b)
  92         comb += equal.eq(a == b)
  93
  94         # They're in reverse bit order because POWER.
  95         # Check V3.0B Book 1, Appendix C.6 for chart
  96         trap_bits = Signal(5)
  97         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  98
  99         # establish if the trap should go ahead (any tests requested in TO)
 100         should_trap = Signal()
 101         comb += should_trap.eq((trap_bits & to).any())
 102
 103         # TODO: some #defines for the bits n stuff.
 104         with m.Switch(op):
 105             #### trap ####
 106             with m.Case(InternalOp.OP_TRAP):
 107                 """
 108                 -- trap instructions (tw, twi, td, tdi)
 109                 if or (trapval and insn_to(e_in.insn)) = '1' then
 110                     -- generate trap-type program interrupt
 111                     exception := '1';
 112                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 113                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 114                     -- set bit 46 to say trap occurred
 115                     ctrl_tmp.srr1(63 - 46) <= '1';
 116                 """
 117                 with m.If(should_trap):
 118                     comb += nia_o.data.eq(0x700)         # trap address
 119                     comb += nia_o.ok.eq(1)
 120                     comb += srr1_o.data.eq(msr_i)   # old MSR
 121                     comb += srr1_o.data[63-46].eq(1)     # XXX which bit?
 122                     comb += srr1_o.ok.eq(1)
 123                     comb += srr0_o.data.eq(cia_i)   # old PC
 124                     comb += srr0_o.ok.eq(1)
 125
 126             # move to SPR
 127             with m.Case(InternalOp.OP_MTMSR):
 128                 # TODO: some of the bits need zeroing?
 129                 """
 130                 if e_in.insn(16) = '1' then  <-- this is X-form field "L".
 131                     -- just update EE and RI
 132                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 133                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 134                 else
 135                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 136                     -- and 63 (LE) (IBM bit numbering)
 137                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 138                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 139                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 140                     if c_in(MSR_PR) = '1' then
 141                         ctrl_tmp.msr(MSR_EE) <= '1';
 142                         ctrl_tmp.msr(MSR_IR) <= '1';
 143                         ctrl_tmp.msr(MSR_DR) <= '1';
 144                 """
 145                 """
 146                 L = self.fields.FormXL.L[0:-1]
 147                 if e_in.insn(16) = '1' then  <-- this is X-form field "L".
 148                 -- just update EE and RI
 149                 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 150                 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 151                 """
 152                 L = self.fields.FormX.L[0:-1]
 153                 with m.If(L):
 154                     comb += msr_o[MSR_EE].eq(msr_i[MSR_EE])
 155                     comb += msr_o[MSR_RI].eq(msr_i[MSR_RI])
 156
 157                 with m.Else():
 158                     for stt, end in [(1,12), (13, 60), (61, 64)]:
 159                         comb += msr_o.data[stt:end].eq(a_i[stt:end])
 160                     with m.If(a[MSR_PR]):
 161                             msr_o[MSR_EE].eq(1)
 162                             msr_o[MSR_IR].eq(1)
 163                             msr_o[MSR_DR].eq(1)
 164                 comb += msr_o.ok.eq(1)
 165
 166             # move from SPR
 167             with m.Case(InternalOp.OP_MFMSR):
 168                 # TODO: some of the bits need zeroing?  apparently not
 169                 """
 170                     when OP_MFMSR =>
 171                         result := ctrl.msr;
 172                         result_en := '1';
 173                 """
 174                 comb += o.data.eq(msr_i)
 175                 comb += o.ok.eq(1)
 176
 177             with m.Case(InternalOp.OP_RFID):
 178                 """
 179                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 180                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 181                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 182                 -- Can't use msr_copy here because the partial function MSR
 183                 -- bits should be left unchanged, not zeroed.
 184                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 185                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 186                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 187                 if b_in(MSR_PR) = '1' then
 188                     ctrl_tmp.msr(MSR_EE) <= '1';
 189                     ctrl_tmp.msr(MSR_IR) <= '1';
 190                     ctrl_tmp.msr(MSR_DR) <= '1';
 191                 end if;
 192                 """
 193                 comb += nia_o.data.eq(br_ext(a_i[2:]))
 194                 comb += nia_o.ok.eq(1)
 195                 for stt, end in [(0,16), (22, 27), (31, 64)]:
 196                     comb += msr_o.data[stt:end].eq(b_i[stt:end])
 197                 with m.If(a[MSR_PR]):
 198                         msr_o[MSR_EE].eq(1)
 199                         msr_o[MSR_IR].eq(1)
 200                         msr_o[MSR_DR].eq(1)
 201                 comb += msr_o.ok.eq(1)
 202
 203             with m.Case(InternalOp.OP_SC):
 204                 """
 205                 # TODO: scv must generate illegal instruction.  this is
 206                 # the decoder's job, not ours, here.
 207                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 208                 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 209                 """
 210                 comb += nia_o.eq(0xC00) # trap address
 211                 comb += nia_o.ok.eq(1)
 212                 comb += srr1_o.data.eq(msr_i)
 213                 comb += srr1_o.ok.eq(1)
 214
 215             # TODO (later)
 216             #with m.Case(InternalOp.OP_ADDPCIS):
 217             #    pass
 218
 219         comb += self.o.ctx.eq(self.i.ctx)
 220
 221         return m