src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.fu.branch.main_stage import br_ext
  13 from soc.decoder.power_enums import InternalOp
  14
  15 from soc.decoder.power_fields import DecodeFields
  16 from soc.decoder.power_fieldsn import SignalBitRange
  17
  18
  19 # Listed in V3.0B Book III Chap 4.2.1
  20 # MSR bit numbers
  21 MSR_SF  = (63 - 0)     # Sixty-Four bit mode
  22 MSR_HV  = (63 - 3)     # Hypervisor state
  23 MSR_S   = (63 - 41)    # Secure state
  24 MSR_EE  = (63 - 48)    # External interrupt Enable
  25 MSR_PR  = (63 - 49)    # PRoblem state
  26 MSR_FP  = (63 - 50)    # FP available
  27 MSR_ME  = (63 - 51)    # Machine Check int enable
  28 MSR_IR  = (63 - 58)    # Instruction Relocation
  29 MSR_DR  = (63 - 59)    # Data Relocation
  30 MSR_PMM = (63 - 60)    # Performance Monitor Mark
  31 MSR_RI  = (63 - 62)    # Recoverable Interrupt
  32 MSR_LE  = (63 - 63)    # Little Endian
  33
  34
  35 def msr_copy(msr_o, msr_i, zero_me=True):
  36     """
  37     -- ISA says this:
  38     --  Defined MSR bits are classified as either full func-
  39     --  tion or partial function. Full function MSR bits are
  40     --  saved in SRR1 or HSRR1 when an interrupt other
  41     --  than a System Call Vectored interrupt occurs and
  42     --  restored by rfscv, rfid, or hrfid, while partial func-
  43     --  tion MSR bits are not saved or restored.
  44     --  Full function MSR bits lie in the range 0:32, 37:41, and
  45     --  48:63, and partial function MSR bits lie in the range
  46     --  33:36 and 42:47. (Note this is IBM bit numbering).
  47     msr_out := (others => '0');
  48     msr_out(63 downto 31) := msr(63 downto 31);
  49     msr_out(26 downto 22) := msr(26 downto 22);
  50     msr_out(15 downto 0)  := msr(15 downto 0);
  51     """
  52     l = []
  53     if zero_me:
  54         l.append(msr_o.eq(0))
  55     for stt, end in [(0,16), (22, 27), (31, 64)]:
  56         l.append(msr_o[stt:end].eq(msr_i[stt:end]))
  57     return l
  58
  59
  60 def msr_check_pr(m, msr_o):
  61     """msr_check_pr: checks "problem state"
  62     """
  63     comb = m.d.comb
  64     with m.If(msrdata[MSR_PR]):
  65         comb += msr[MSR_EE].eq(1) # set external interrupt bit
  66         comb += msr[MSR_IR].eq(1) # set instruction relocation bit
  67         comb += msr[MSR_DR].eq(1) # set data relocation bit
  68
  69
  70 class TrapMainStage(PipeModBase):
  71     def __init__(self, pspec):
  72         super().__init__(pspec, "main")
  73         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  74         self.fields.create_specs()
  75
  76     def trap(self, m, return_addr, trap_addr):
  77         """trap """ # TODO add descriptive docstring
  78         comb  = m.d.comb
  79         nia_o, srr0_o = self.o.nia, self.o.srr0 # add srr1 as well
  80
  81         # trap address
  82         comb += nia_o.data.eq(trap_addr)
  83         comb += nia_o.ok.eq(1)
  84
  85         # addr to begin from on return
  86         comb += srr0_o.data.eq(return_addr)
  87         comb += srr0_o.ok.eq(1)
  88
  89         # TODO: MSR (into srr1)
  90
  91     def ispec(self):
  92         return TrapInputData(self.pspec)
  93
  94     def ospec(self):
  95         return TrapOutputData(self.pspec)
  96
  97     def elaborate(self, platform):
  98         m = Module()
  99         comb = m.d.comb
 100         op = self.i.ctx.op
 101
 102         # convenience variables
 103         a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
 104         o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
 105         srr0_o, srr1_o = self.o.srr0, self.o.srr1
 106
 107         # take copy of D-Form TO field
 108         i_fields = self.fields.FormD
 109         to = Signal(i_fields.TO[0:-1].shape())
 110         comb += to.eq(i_fields.TO[0:-1])
 111
 112         # signed/unsigned temporaries for RA and RB
 113         a_s = Signal(signed(64), reset_less=True)
 114         b_s = Signal(signed(64), reset_less=True)
 115
 116         a = Signal(64, reset_less=True)
 117         b = Signal(64, reset_less=True)
 118
 119         # set up A and B comparison (truncate/sign-extend if 32 bit)
 120         with m.If(op.is_32bit):
 121             comb += a_s.eq(exts(a_i, 32, 64))
 122             comb += b_s.eq(exts(b_i, 32, 64))
 123             comb += a.eq(a_i[0:32])
 124             comb += b.eq(b_i[0:32])
 125         with m.Else():
 126             comb += a_s.eq(a_i)
 127             comb += b_s.eq(b_i)
 128             comb += a.eq(a_i)
 129             comb += b.eq(b_i)
 130
 131         # establish comparison bits
 132         lt_s = Signal(reset_less=True)
 133         gt_s = Signal(reset_less=True)
 134         lt_u = Signal(reset_less=True)
 135         gt_u = Signal(reset_less=True)
 136         equal = Signal(reset_less=True)
 137
 138         comb += lt_s.eq(a_s < b_s)
 139         comb += gt_s.eq(a_s > b_s)
 140         comb += lt_u.eq(a < b)
 141         comb += gt_u.eq(a > b)
 142         comb += equal.eq(a == b)
 143
 144         # They're in reverse bit order because POWER.
 145         # Check V3.0B Book 1, Appendix C.6 for chart
 146         trap_bits = Signal(5)
 147         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
 148
 149         # establish if the trap should go ahead (any tests requested in TO)
 150         should_trap = Signal()
 151         comb += should_trap.eq((trap_bits & to).any())
 152
 153         # TODO: some #defines for the bits n stuff.
 154         with m.Switch(op):
 155             #### trap ####
 156             with m.Case(InternalOp.OP_TRAP):
 157                 # trap instructions (tw, twi, td, tdi)
 158                 with m.If(should_trap):
 159                     # generate trap-type program interrupt
 160
 161                     # change the PC to trap address 0x700
 162                     comb += nia_o.data.eq(0x700)         # trap address
 163                     comb += nia_o.ok.eq(1)
 164
 165                     # take a copy of the current MSR in SRR1
 166                     comb += msr_copy(srr1_o.data, msr_i)   # old MSR
 167                     # set bit 46 to say trap occurred
 168                     comb += srr1_o.data[63-46].eq(1)     # XXX which bit?
 169                     comb += srr1_o.ok.eq(1)
 170
 171                     # take a copy of the current PC in SRR0
 172                     comb += srr0_o.data.eq(cia_i)   # old PC
 173                     comb += srr0_o.ok.eq(1)
 174
 175             # move to MSR
 176             with m.Case(InternalOp.OP_MTMSR):
 177                 L = self.fields.FormX.L[0:-1] # X-Form field L
 178                 with m.If(L):
 179                     # just update EE and RI
 180                     comb += msr_o.data[MSR_EE].eq(a_i[MSR_EE])
 181                     comb += msr_o.data[MSR_RI].eq(a_i[MSR_RI])
 182                 with m.Else():
 183                     # Architecture says to leave out bits 3 (HV), 51 (ME)
 184                     # and 63 (LE) (IBM bit numbering)
 185                     for stt, end in [(1,12), (13, 60), (61, 64)]:
 186                         comb += msr_o.data[stt:end].eq(a_i[stt:end])
 187                     msr_check_pr(m, msr_o.data)
 188                 comb += msr_o.ok.eq(1)
 189
 190             # move from MSR
 191             with m.Case(InternalOp.OP_MFMSR):
 192                 # TODO: some of the bits need zeroing?  apparently not
 193                 comb += o.data.eq(msr_i)
 194                 comb += o.ok.eq(1)
 195
 196             with m.Case(InternalOp.OP_RFID):
 197                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 198                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 199
 200                 # return addr was in srr0
 201                 comb += nia_o.data.eq(br_ext(srr0_i[2:]))
 202                 comb += nia_o.ok.eq(1)
 203                 # MSR was in srr1
 204                 comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
 205                 msr_check_pr(m, msr_o.data)
 206                 comb += msr_o.ok.eq(1)
 207
 208             with m.Case(InternalOp.OP_SC):
 209                 # TODO: scv must generate illegal instruction.  this is
 210                 # the decoder's job, not ours, here.
 211
 212                 # jump to the trap address
 213                 comb += nia_o.eq(0xC00) # trap address
 214                 comb += nia_o.ok.eq(1)
 215                 # keep a copy of the MSR in SRR1
 216                 comb += msr_copy(srr1_o.data, msr_i)
 217                 comb += srr1_o.ok.eq(1)
 218                 # and store the (next-after-return) PC in SRR0
 219                 comb += srr0_o.data.eq(cia_i+4) # addr to begin from on return
 220                 comb += srr0_o.ok.eq(1)
 221
 222             # TODO (later)
 223             #with m.Case(InternalOp.OP_ADDPCIS):
 224             #    pass
 225
 226         comb += self.o.ctx.eq(self.i.ctx)
 227
 228         return m