src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.decoder.power_enums import InternalOp
  13
  14 from soc.decoder.power_fields import DecodeFields
  15 from soc.decoder.power_fieldsn import SignalBitRange
  16
  17 # TODO at some point move these to their own module (for use elsewhere)
  18 """
  19     -- MSR bit numbers
  20     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  21     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  22     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  23     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  24     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  25     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  26     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  27 """
  28
  29 class TrapMainStage(PipeModBase):
  30     def __init__(self, pspec):
  31         super().__init__(pspec, "main")
  32         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  33         self.fields.create_specs()
  34
  35     def ispec(self):
  36         return TrapInputData(self.pspec)
  37
  38     def ospec(self):
  39         return TrapOutputData(self.pspec)
  40
  41     def elaborate(self, platform):
  42         m = Module()
  43         comb = m.d.comb
  44         op = self.i.ctx.op
  45         a_i, b_i = self.i.a, self.i.b
  46
  47         # take copy of D-Form TO field
  48         i_fields = self.fields.FormD
  49         to = Signal(i_fields.TO[0:-1].shape())
  50         comb += to.eq(i_fields.TO[0:-1])
  51
  52         # signed/unsigned temporaries for RA and RB
  53         a_s = Signal(signed(64), reset_less=True)
  54         b_s = Signal(signed(64), reset_less=True)
  55
  56         a = Signal(64, reset_less=True)
  57         b = Signal(64, reset_less=True)
  58
  59         # set up A and B comparison (truncate/sign-extend if 32 bit)
  60         with m.If(op.is_32bit):
  61             comb += a_s.eq(exts(a_i, 32, 64))
  62             comb += b_s.eq(exts(b_i, 32, 64))
  63             comb += a.eq(a_i[0:32])
  64             comb += b.eq(b_i[0:32])
  65         with m.Else():
  66             comb += a_s.eq(a_i)
  67             comb += b_s.eq(b_i)
  68             comb += a.eq(a_i)
  69             comb += b.eq(b_i)
  70
  71         # establish comparison bits
  72         lt_s = Signal(reset_less=True)
  73         gt_s = Signal(reset_less=True)
  74         lt_u = Signal(reset_less=True)
  75         gt_u = Signal(reset_less=True)
  76         equal = Signal(reset_less=True)
  77
  78         comb += lt_s.eq(a_s < b_s)
  79         comb += gt_s.eq(a_s > b_s)
  80         comb += lt_u.eq(a < b)
  81         comb += gt_u.eq(a > b)
  82         comb += equal.eq(a == b)
  83
  84         # They're in reverse bit order because POWER.
  85         # Check V3.0B Book 1, Appendix C.6 for chart
  86         trap_bits = Signal(5)
  87         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  88
  89         # establish if the trap should go ahead (any tests requested in TO)
  90         should_trap = Signal()
  91         comb += should_trap.eq((trap_bits & to).any())
  92
  93         # TODO: some #defines for the bits n stuff.
  94         with m.Switch(op):
  95             #### trap ####
  96             with m.Case(InternalOp.OP_TRAP):
  97                 """
  98                 -- trap instructions (tw, twi, td, tdi)
  99                 if or (trapval and insn_to(e_in.insn)) = '1' then
 100                     -- generate trap-type program interrupt
 101                     exception := '1';
 102                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 103                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 104                     -- set bit 46 to say trap occurred
 105                     ctrl_tmp.srr1(63 - 46) <= '1';
 106                 """
 107                 with m.If(should_trap):
 108                     comb += self.o.nia.data.eq(0x700)         # trap address
 109                     comb += self.o.nia.ok.eq(1)
 110                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
 111                     comb += self.o.srr1.data[63-46].eq(1)     # XXX which bit?
 112                     comb += self.o.srr1.ok.eq(1)
 113                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
 114                     comb += self.o.srr0.ok.eq(1)
 115
 116             # move to SPR
 117             with m.Case(InternalOp.OP_MTMSR):
 118                 # TODO: some of the bits need zeroing?
 119                 """
 120                 if e_in.insn(16) = '1' then
 121                     -- just update EE and RI
 122                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 123                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 124                 else
 125                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 126                     -- and 63 (LE) (IBM bit numbering)
 127                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 128                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 129                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 130                     if c_in(MSR_PR) = '1' then
 131                         ctrl_tmp.msr(MSR_EE) <= '1';
 132                         ctrl_tmp.msr(MSR_IR) <= '1';
 133                         ctrl_tmp.msr(MSR_DR) <= '1';
 134                 """
 135                 comb += self.o.msr.data.eq(a)
 136                 comb += self.o.msr.ok.eq(1)
 137
 138             # move from SPR
 139             with m.Case(InternalOp.OP_MFMSR):
 140                 # TODO: some of the bits need zeroing?  apparently not
 141                 """
 142                     when OP_MFMSR =>
 143                         result := ctrl.msr;
 144                         result_en := '1';
 145                 """
 146                 comb += self.o.o.data.eq(self.i.msr)
 147                 comb += self.o.o.ok.eq(1)
 148
 149             # TODO
 150             with m.Case(InternalOp.OP_RFID):
 151                 """
 152                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 153                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 154                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 155                 -- Can't use msr_copy here because the partial function MSR
 156                 -- bits should be left unchanged, not zeroed.
 157                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 158                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 159                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 160                 if b_in(MSR_PR) = '1' then
 161                     ctrl_tmp.msr(MSR_EE) <= '1';
 162                     ctrl_tmp.msr(MSR_IR) <= '1';
 163                     ctrl_tmp.msr(MSR_DR) <= '1';
 164                 end if;
 165                 """
 166                 pass
 167
 168             # TODO
 169             with m.Case(InternalOp.OP_SC):
 170                 """
 171                 # TODO: scv must generate illegal instruction.  this is
 172                 # the decoder's job, not ours, here.
 173                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 174                 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 175                 """
 176                 pass
 177
 178             #with m.Case(InternalOp.OP_ADDPCIS):
 179             #    pass
 180
 181         comb += self.o.ctx.eq(self.i.ctx)
 182
 183         return m