src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.fu.branch.main_stage import br_ext
  13 from soc.decoder.power_enums import InternalOp
  14
  15 from soc.decoder.power_fields import DecodeFields
  16 from soc.decoder.power_fieldsn import SignalBitRange
  17
  18 # TODO at some point move these to their own module (for use elsewhere)
  19 # TODO: turn these into python constants (just "MSR_SF = 63-0 # comment" etc.)
  20 """
  21     Listed in V3.0B Book III Chap 4.2.1
  22     -- MSR bit numbers
  23     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  24     constant MSR_HV  : integer := (63 - 3);     -- Hypervisor state
  25     constant MSR_S   : integer := (63 - 41);    -- Secure state
  26     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  27     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  28     constant MSR_FP  : integer := (63 - 50);    -- FP available
  29     constant MSR_ME  : integer := (63 - 51);    -- Machine Check int enable
  30     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  31     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  32     constant MSR_PMM : integer := (63 - 60);    -- Performance Monitor Mark
  33     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  34     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  35 """
  36
  37 class TrapMainStage(PipeModBase):
  38     def __init__(self, pspec):
  39         super().__init__(pspec, "main")
  40         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  41         self.fields.create_specs()
  42
  43     def ispec(self):
  44         return TrapInputData(self.pspec)
  45
  46     def ospec(self):
  47         return TrapOutputData(self.pspec)
  48
  49     def elaborate(self, platform):
  50         m = Module()
  51         comb = m.d.comb
  52         op = self.i.ctx.op
  53         a_i, b_i = self.i.a, self.i.b
  54
  55         # take copy of D-Form TO field
  56         i_fields = self.fields.FormD
  57         to = Signal(i_fields.TO[0:-1].shape())
  58         comb += to.eq(i_fields.TO[0:-1])
  59
  60         # signed/unsigned temporaries for RA and RB
  61         a_s = Signal(signed(64), reset_less=True)
  62         b_s = Signal(signed(64), reset_less=True)
  63
  64         a = Signal(64, reset_less=True)
  65         b = Signal(64, reset_less=True)
  66
  67         # set up A and B comparison (truncate/sign-extend if 32 bit)
  68         with m.If(op.is_32bit):
  69             comb += a_s.eq(exts(a_i, 32, 64))
  70             comb += b_s.eq(exts(b_i, 32, 64))
  71             comb += a.eq(a_i[0:32])
  72             comb += b.eq(b_i[0:32])
  73         with m.Else():
  74             comb += a_s.eq(a_i)
  75             comb += b_s.eq(b_i)
  76             comb += a.eq(a_i)
  77             comb += b.eq(b_i)
  78
  79         # establish comparison bits
  80         lt_s = Signal(reset_less=True)
  81         gt_s = Signal(reset_less=True)
  82         lt_u = Signal(reset_less=True)
  83         gt_u = Signal(reset_less=True)
  84         equal = Signal(reset_less=True)
  85
  86         comb += lt_s.eq(a_s < b_s)
  87         comb += gt_s.eq(a_s > b_s)
  88         comb += lt_u.eq(a < b)
  89         comb += gt_u.eq(a > b)
  90         comb += equal.eq(a == b)
  91
  92         # They're in reverse bit order because POWER.
  93         # Check V3.0B Book 1, Appendix C.6 for chart
  94         trap_bits = Signal(5)
  95         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  96
  97         # establish if the trap should go ahead (any tests requested in TO)
  98         should_trap = Signal()
  99         comb += should_trap.eq((trap_bits & to).any())
 100
 101         # TODO: some #defines for the bits n stuff.
 102         with m.Switch(op):
 103             #### trap ####
 104             with m.Case(InternalOp.OP_TRAP):
 105                 """
 106                 -- trap instructions (tw, twi, td, tdi)
 107                 if or (trapval and insn_to(e_in.insn)) = '1' then
 108                     -- generate trap-type program interrupt
 109                     exception := '1';
 110                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 111                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 112                     -- set bit 46 to say trap occurred
 113                     ctrl_tmp.srr1(63 - 46) <= '1';
 114                 """
 115                 with m.If(should_trap):
 116                     comb += self.o.nia.data.eq(0x700)         # trap address
 117                     comb += self.o.nia.ok.eq(1)
 118                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
 119                     comb += self.o.srr1.data[63-46].eq(1)     # XXX which bit?
 120                     comb += self.o.srr1.ok.eq(1)
 121                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
 122                     comb += self.o.srr0.ok.eq(1)
 123
 124             # move to SPR
 125             with m.Case(InternalOp.OP_MTMSR):
 126                 # TODO: some of the bits need zeroing?
 127                 """
 128                 if e_in.insn(16) = '1' then  <-- this is X-form field "L".
 129                     -- just update EE and RI
 130                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 131                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 132                 else
 133                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 134                     -- and 63 (LE) (IBM bit numbering)
 135                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 136                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 137                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 138                     if c_in(MSR_PR) = '1' then
 139                         ctrl_tmp.msr(MSR_EE) <= '1';
 140                         ctrl_tmp.msr(MSR_IR) <= '1';
 141                         ctrl_tmp.msr(MSR_DR) <= '1';
 142                 """
 143                 L = self.fields.FormX.L[0:-1]
 144                 with m.If(L):
 145                     comb += self.o.msr[MSR_EE].eq(self.i.msr[MSR_EE])
 146                     comb += self.o.msr[MSR_RI].eq(self.i.msr[MSR_RI])
 147
 148                 with m.Else():
 149                     for stt, end in [(1,12), (13, 60), (61, 64)]:
 150                         comb += self.o.msr.data[stt:end].eq(a[stt:end])
 151                     with m.If(a[MSR_PR]):
 152                             self.o.msr[MSR_EE].eq(1)
 153                             self.o.msr[MSR_IR].eq(1)
 154                             self.o.msr[MSR_DR].eq(1)
 155                 comb += self.o.msr.ok.eq(1)
 156
 157             # move from SPR
 158             with m.Case(InternalOp.OP_MFMSR):
 159                 # TODO: some of the bits need zeroing?  apparently not
 160                 """
 161                     when OP_MFMSR =>
 162                         result := ctrl.msr;
 163                         result_en := '1';
 164                 """
 165                 comb += self.o.o.data.eq(self.i.msr)
 166                 comb += self.o.o.ok.eq(1)
 167
 168             with m.Case(InternalOp.OP_RFID):
 169                 """
 170                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 171                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 172                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 173                 -- Can't use msr_copy here because the partial function MSR
 174                 -- bits should be left unchanged, not zeroed.
 175                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 176                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 177                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 178                 if b_in(MSR_PR) = '1' then
 179                     ctrl_tmp.msr(MSR_EE) <= '1';
 180                     ctrl_tmp.msr(MSR_IR) <= '1';
 181                     ctrl_tmp.msr(MSR_DR) <= '1';
 182                 end if;
 183                 """
 184                 comb += self.o.nia.data.eq(br_ext(a[63:1] & 0))
 185                 comb += self.o.nia.ok.eq(1)
 186                 for stt, end in [(0,16), (22, 27), (31, 64)]:
 187                     comb += self.o.msr.data[stt:end].eq(a[stt:end])
 188                 with m.If(a[MSR_PR]):
 189                         self.o.msr[MSR_EE].eq(1)
 190                         self.o.msr[MSR_IR].eq(1)
 191                         self.o.msr[MSR_DR].eq(1)
 192                 comb += self.o.msr.ok.eq(1)
 193
 194             with m.Case(InternalOp.OP_SC):
 195                 """
 196                 # TODO: scv must generate illegal instruction.  this is
 197                 # the decoder's job, not ours, here.
 198                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 199                 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 200                 """
 201                 comb += self.o.nia.eq(0xC00) # trap address
 202                 comb += self.o.nia.ok.eq(1)
 203                 comb += self.o.srr1.data.eq(self.i.msr)
 204                 comb += self.o.srr1.ok.eq(1)
 205
 206             # TODO (later)
 207             #with m.Case(InternalOp.OP_ADDPCIS):
 208             #    pass
 209
 210         comb += self.o.ctx.eq(self.i.ctx)
 211
 212         return m