src/soc/fu/trap/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5 from nmutil.dynamicpipe import SimpleHandshakeRedir
   6 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
   7
   8
   9 class TrapInputData(IntegerData):
  10     regspec = [('INT', 'ra', '0:63'),
  11                ('INT', 'rb', '0:63'),
  12                ('FAST', 'spr1', '0:63'),
  13                ('FAST', 'cia', '0:63'),
  14                ('FAST', 'msr', '0:63')]
  15     def __init__(self, pspec):
  16         super().__init__(pspec)
  17         self.ra = Signal(64, reset_less=True)  # RA
  18         self.rb = Signal(64, reset_less=True)  # RB/immediate
  19         self.spr1 = Data(64, name="spr1") # SRR0
  20         self.cia = Signal(64, reset_less=True)  # Program counter
  21         self.msr = Signal(64, reset_less=True)  # MSR
  22         # convenience
  23         self.srr0, self.a, self.b = self.spr1, self.ra, self.rb
  24
  25     def __iter__(self):
  26         yield from super().__iter__()
  27         yield self.ra
  28         yield self.rb
  29         yield self.spr1
  30         yield self.cia
  31         yield self.msr
  32
  33     def eq(self, i):
  34         lst = super().eq(i)
  35         return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.spr1.eq(i.spr1),
  36                       self.cia.eq(i.cia), self.msr.eq(i.msr)]
  37
  38
  39 class TrapOutputData(IntegerData):
  40     regspec = [('INT', 'o', '0:63'),
  41                ('FAST', 'spr1', '0:63'),
  42                ('FAST', 'spr2', '0:63'),
  43                ('FAST', 'nia', '0:63'),
  44                ('FAST', 'msr', '0:63')]
  45     def __init__(self, pspec):
  46         super().__init__(pspec)
  47         self.o = Data(64, name="o")       # RA
  48         self.spr1 = Data(64, name="spr1") # SRR0 SPR
  49         self.spr2 = Data(64, name="spr2") # SRR1 SPR
  50         self.nia = Data(64, name="nia") # NIA (Next PC)
  51         self.msr = Data(64, name="msr") # MSR
  52         # convenience
  53         self.srr0, self.srr1 = self.spr1, self.spr2
  54
  55     def __iter__(self):
  56         yield from super().__iter__()
  57         yield self.o
  58         yield self.nia
  59         yield self.msr
  60         yield self.spr1
  61         yield self.spr2
  62
  63     def eq(self, i):
  64         lst = super().eq(i)
  65         return lst + [ self.o.eq(i.o), self.nia.eq(i.nia), self.msr.eq(i.msr),
  66                       self.spr1.eq(i.spr1), self.spr2.eq(i.spr2)]
  67
  68
  69 # TODO: replace CompALUOpSubset with CompTrapOpSubset
  70 class TrapPipeSpec:
  71     regspec = (TrapInputData.regspec, TrapOutputData.regspec)
  72     opsubsetkls = CompALUOpSubset
  73     def __init__(self, id_wid, op_wid):
  74         self.id_wid = id_wid
  75         self.op_wid = op_wid
  76         self.opkls = lambda _: self.opsubsetkls(name="op")
  77         self.stage = None
  78         self.pipekls = SimpleHandshakeRedir