replace PartitionedSignal with SimdSignal
[soc.git] / src / soc / fu / trap / pipe_data.py
1 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
2 from soc.fu.trap.trap_input_record import CompTrapOpSubset
3
4
5 class TrapInputData(IntegerData):
6 regspec = [('INT', 'ra', '0:63'), # RA
7 ('INT', 'rb', '0:63'), # RB/immediate
8 ('FAST', 'fast1', '0:63'), # SRR0
9 ('FAST', 'fast2', '0:63'), # SRR1
10 ('FAST', 'cia', '0:63'), # Program counter (current)
11 ('FAST', 'msr', '0:63')] # MSR
12 def __init__(self, pspec):
13 super().__init__(pspec, False)
14 # convenience
15 self.srr0, self.srr1 = self.fast1, self.fast2
16 self.a, self.b = self.ra, self.rb
17
18
19 class TrapOutputData(IntegerData):
20 regspec = [('INT', 'o', '0:63'), # RA
21 ('FAST', 'fast1', '0:63'), # SRR0 SPR
22 ('FAST', 'fast2', '0:63'), # SRR1 SPR
23 ('FAST', 'nia', '0:63'), # NIA (Next PC)
24 ('FAST', 'msr', '0:63')] # MSR
25 def __init__(self, pspec):
26 super().__init__(pspec, True)
27 # convenience
28 self.srr0, self.srr1 = self.fast1, self.fast2
29
30
31
32 class TrapPipeSpec(CommonPipeSpec):
33 regspec = (TrapInputData.regspec, TrapOutputData.regspec)
34 opsubsetkls = CompTrapOpSubset