src/soc/fu/trap/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.alu.pipe_data import IntegerData
   4 from soc.decoder.power_decoder2 import Data
   5
   6
   7 class TrapInputData(IntegerData):
   8     def __init__(self, pspec):
   9         super().__init__(pspec)
  10         self.a = Signal(64, reset_less=True)  # RA
  11         self.b = Signal(64, reset_less=True)  # RB/immediate
  12         self.cia = Signal(64, reset_less=True)  # Program counter
  13         self.msr = Signal(64, reset_less=True)  # MSR
  14
  15     def __iter__(self):
  16         yield from super().__iter__()
  17         yield self.a
  18         yield self.b
  19         yield self.cia
  20         yield self.msr
  21
  22     def eq(self, i):
  23         lst = super().eq(i)
  24         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  25                       self.cia.eq(i.nia), self.msr.eq(i.msr)]
  26
  27
  28 class TrapOutputData(IntegerData):
  29     def __init__(self, pspec):
  30         super().__init__(pspec)
  31         self.nia = Data(64, name="nia") # NIA (Next PC)
  32         self.msr = Signal(64, reset_less=True) # MSR
  33         self.srr0 = Data(64, name="srr0") # SRR0 SPR
  34         self.srr1 = Data(64, name="srr1") # SRR1 SPR
  35
  36     def __iter__(self):
  37         yield from super().__iter__()
  38         yield self.nia
  39         yield self.msr
  40         yield self.srr0
  41         yield self.srr1
  42
  43     def eq(self, i):
  44         lst = super().eq(i)
  45         return lst + [ self.nia.eq(i.nia), self.msr.eq(i.msr),
  46                       self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)]